Talks and Seminars


Upcoming Events

InvasIC Seminar, October 5, 2017 at FAU:
Applying Model-Driven Engineering in the co-design of Real-Time Embedded Systems

Prof. Marco Wehrmeister (Federal University of Technology - Parana)

This talk will present methods and techniques applied in the co-design of real-time embedded systems, specifically those that are implemented as a System-on-Chip (SoC) that includes components with reconfigurable logic (FPGA). The target application domain is automation systems. The main objective is to discuss techniques and methods that use high-level abstractions, such as UML/MARTE models and concepts of the Aspect-Oriented Software Development (AOSD), for an integrated co-design addressing both software and hardware design. To this end, we will introduce model-driven engineering (MDE) techniques combined with separation of concerns in the handling of functional and non-functional requirements. Automatic transformations between models allow the information specified in different high-level modeling languages to be integrated and shared within the (co-)design of the hardware and software components. To illustrate such transformations, code generation techniques will be presented for software components (e.g., java and C / C++) and hardware (VHDL) applied in a case study that represents a real application. Results indicate that the abstraction increase obtained by using MDE and the separation of concerns leads to an improvement in the reuse and adaptation of software components. Thus, by applying these ideas in the design of hardware components in FPGA, one can obtain similar benefits.


Annual Meeting 2017, September 20-21, 2017, Neu-Ulm:

Projects and working groups will present the status of their work in short talks. The second topic of the meeting will be the ideas for the third funding phase. The Annual Meeting will be held in Neu-Ulm Orange Hotel und Apartments.


Invited Talk, November 14, 2017:
Application Mapping Methodologies for NoC-Based MPSOCs

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Dr.-Ing. Jürgen Teich will give an invited talk at the University of California, Irvine, USA: In this talk, he will give an overview of novel techniques for mapping applications to NoC-based multi-core architectures (MPSoCs). Complex applications requiring hetergenous processing resources are often described by task graphs with data dependencies. Here, the nodes represent actors which are typically executed periodically based on the availability of data. One prominent example of applications is stream processing. Here, it is important to guarantee either bandwidth or execution time requirements, but also security aspects, energy and reliability often impose constraints on the mapping of the tasks as well as the communication to cores, respectively the underlying NoC. Concerning mapping applications, we first present solutions based on self-embedding. The idea is here that a source node issues request to find appropriate resources for the sucessor tasks, and so on. The next class of techniques is called Hybrid Application Mapping (HAM). Here, a careful analysis and characterization of symmetric mappings to constellations of cores and routes is explored in a static phase of design space exploration. At run-time, the operating system then only searches for such constellations to be available for finding a concrete mapping. We present ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that deadlines or throughput requirements will be automatically guaranteed for streaming applications. Finally, we also discuss resource constellations such are able to satisfy certain securit requirements on an MPSoC.

Invited Talk, November 15, 2017:
Generating FPGA-based Image Processing Accelerators with Hipacc

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Dr.-Ing. Jürgen Teich will give an invited talk at International Conference on Computer Aided Design (ICCAD 2017), Irvine, USA: Domain-Specific Languages (DSLs) provide a high-level and domainspecific abstraction to concisely describe algorithms within a certain domain. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs became an attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGAs have been proven to be among the most suitable architectures. In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.

Past Events

Internal Meetings: Internal Meetings of the CRC/Transregio 89
Trainings and Tutorials: Trainings and Tutorials for Doctoral Researchers, Seminars for High School Pupils and Summer Schools
Activities: InvasIC Seminars and Invited Talks