InvasIC News & Activities


Events 2017

Invited Talk, November 15, 2017:
Generating FPGA-based Image Processing Accelerators with Hipacc

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Dr.-Ing. Jürgen Teich gave an invited talk at International Conference on Computer Aided Design (ICCAD 2017), Irvine, USA: Domain-Specific Languages (DSLs) provide a high-level and domainspecific abstraction to concisely describe algorithms within a certain domain. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs became an attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGAs have been proven to be among the most suitable architectures. In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.

Invited Talk, November 14, 2017:
Application Mapping Methodologies for NoC-Based MPSOCs

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Dr.-Ing. Jürgen Teich will give an invited talk at the University of California, Irvine, USA: In this talk, he gave an overview of novel techniques for mapping applications to NoC-based multi-core architectures (MPSoCs). Complex applications requiring hetergenous processing resources are often described by task graphs with data dependencies. Here, the nodes represent actors which are typically executed periodically based on the availability of data. One prominent example of applications is stream processing. Here, it is important to guarantee either bandwidth or execution time requirements, but also security aspects, energy and reliability often impose constraints on the mapping of the tasks as well as the communication to cores, respectively the underlying NoC. Concerning mapping applications, we first present solutions based on self-embedding. The idea is here that a source node issues request to find appropriate resources for the sucessor tasks, and so on. The next class of techniques is called Hybrid Application Mapping (HAM). Here, a careful analysis and characterization of symmetric mappings to constellations of cores and routes is explored in a static phase of design space exploration. At run-time, the operating system then only searches for such constellations to be available for finding a concrete mapping. We present ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that deadlines or throughput requirements will be automatically guaranteed for streaming applications. Finally, we also discuss resource constellations such are able to satisfy certain securit requirements on an MPSoC.

Invasive computing joins the open house event at TUM

Oct. 21, 2017, Garching: Emily Mo-Hellenbrand (TUM) demonstrated invasive computing at the open house event. more information

Outstanding Paper Award and Best Presentation Award

October 6, 2017, Grenoble, France:

Picture of Behnaz Pourmohseni receiving the Best Presentation Award Award Certificate Behnaz Pourmohseni, Dr.-Ing. Stefan Wildermann, Prof. Dr.-Ing. Michael Glaß and Prof. Dr.-Ing. Jürgen Teich received the Outstanding Paper Award for their contribution "Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems" at the International Conference on Real-Time Networks and Systems, Grenoble, France. In addition, Behnaz Pourmohseni received the Best Presentation Award. more information


30th IEEE International System-On-Chip Conference (SoCC) 2017

Sep. 7, 2017, Munich: Prof. Jörg Henkel (KIT) gave a keynote on "The Triangle of Power Density, Circuit Degradation and Reliability".
Power density will stay a major challenge for the foreseeable future. Despite orders-of-magnitude-improved efficiency, power consumption per area is sharply rising, mainly due to the limits of voltage scaling. To investigate the physical implications of high power densities, we must distinguish between peak and average temperatures and temporal and spatial thermal gradients because they trigger circuit-aging mechanisms and eventually jeopardize the reliability of an on-chip system.
The talk started by presenting some basic interdependencies in the triangle of power density, circuit degradation and reliability and continued with some solutions to mitigate the problem via, among others, power density-aware resource management and efficient power budgeting. more information

30th IEEE International System-On-Chip Conference (SoCC) 2017

Sep. 5-8, 2017, Munich: Prof. Dr.-Ing. Jürgen Becker (KIT) serves as General Chair and Prof. Dr.-Ing. Ulf Schlichtmann (TUM) as Co-Generals Chair of the 30th IEEE International System-On-Chip Conference (SoCC) 2017 in Munich.
more information

Invited Talk, July 21, 2017, at University of Zürich, Switzerland:
Resource Awareness on Heterogeneous MPSoCs for Image Processing

Prof. Dr.-Ing. Walter Stechele (Integrated Systems, TUM)

Multiprocessor System-on-Chip (MPSoC) offers a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding heterogeneous accelerators and specialized hardware with instruction-set extensions. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, especially with respect to predictability in best effort processing. We investigate the benefits of a resource-aware programming model called Invasive Computing for dynamically mapping image processing applications to different types of PEs available on a heterogeneous MPSoC.

GPU Course "Programming and optimizing for heterogeneous CPU-GPU architectures"

May 15-19, 2017, Munich: Prof. Walter Stechele (TUM) organizes the GPU Course "Programming and optimizing for heterogeneous CPU-GPU architectures" at TUM.
The imminent future of parallel architectures is a tighter integration of different types of processing cores, namely CPUs and GPUs. In this course, you will be introduced to the current heterogeneous architectures, and how to program them using mainstream languages, such as CUDA and OpenCL, and higher level languages as C++AMP.
more information

Transfer project "Integration and Coupling of Tightly Coupled Processor Arrays"

April 27, 2017: Dr. Frank Hannig and Prof. Jürgen Teich received a considerable funding from the DFG for their new transfer project (T1), which is part of the CRC/Transregio 89 from now on. In cooperation with their industry partner Infineon Technologies AG they research the topic "Integration and Coupling of Tightly Coupled Processor Arrays".
Objective of this transfer project is the analysis of massively parallel accelerator architectures, in particular tightly coupled processor arrays (TCPAs), and their integration into a commercial state-of-the-art embedded microcontroller architecture such as Infineon’s AURIX, or ARM’s Cortex-A series of processors.
See transfer project for more information.

Invasive Computing at the Hannover Messe

April 24-28, 2017: Invasive Computing at the Hannover Messe 2017
At this year's Hannover Messe, Éricles Sousa showcased how Invasive Computing can be used to enforce timing predictability on multi-core systems. Here are some impressions from the fair.

Dr. Santiago Pagani has been awarded the ACM "Paul Caspi Memorial Dissertation Award"

April 19, 2017, Pittsburgh:

Picture of Dr. Santiago Pagani receiving the Paul Caspi Memorial Dissertation Award Award Certificate
Dr. Santiago Pagani (KIT) has been awarded the ACM "Paul Caspi Memorial Dissertation Award" from SIGBED (Special Interest Group Embedded Systems of ACM) for his PhD thesis entitled "Power, Energy, and Thermal Management for Clustered Manycores". The award description reads: "The award recognizes outstanding doctoral dissertations that significantly advance the state of the art in the science of embedded systems, in the spirit and legacy of Dr. Paul Caspi's work". The award includes a certificate for the author and an honorarium of 2000 USD. Dr. Pagani received the award at the recent Cyber-Physical Systems Week (CPSWeek) in Pittsburg that took place from April 18-21, 2017. The photo shows Dr. Pagani at the award ceremony on Wed. April 19th in Pittsburgh.

Joint workshop "InvasIC meets HAEC"

January 17/18, 2017: InvasIC meets HAEC Gruppenbild
SFB 89 "Invasive Computing" and SFB 912 "Highly Adaptive Energy-Efficient Computing" organised a joint workshop in Dresden. Researchers from both SFBs met at Schloss Eckberg. to discuss similarities and differences between the two research groups for two days. As coordinators of the two collaborative research centers Prof. Gerhard Fettweis and Prof. Jürgen Teich, gave an interesting overview when having their opening talks in the first evening. On the second day, researchers from both groups presented ideas and results on the following topics:
- energy efficiency
- power stability
- security
- resilience.
The meeting was very intense with lively discussions and useful dialogues between researchers from InvasIC and HAEC.

Events 2016

it - Information Technology: Thematic Issue on "Invasive Computing"

Dezember, 2016: In the current edition of the journal "it - Information Technology" a Thematic Issue on "Invasive Computing" was published. Four articles were written by members of the CRC/Transregio showing different aspects of our work. Prof. Dustar from TU Wien completed the topic with his article on "Elastic computing".
more information

Third Workshop on Low-Power Dependable Computing (LPDC)

November 2016, Hangzhou, China: Dr. Muhammad Shafique (Karlsruher Institut für Technologie, Germany), Prof. Dr. Xiaomin Zhu (National University of Defense Technology, China) and Prof. Dr. Dakai Zhu (University of Texas at San Antonio, USA) organized the Third Workshop on Low-Power Dependable Computing (LPDC) in conjunction with the 2016 International Green and Sustainable Computing Conference (IGSC) in Hangzhou, China.
more information

Dagstuhl Seminar 16441 "Adaptive Isolation for Predictability and Security"

Dagstuhl Gruppenbild
October 30-November 4, 2016, Dagstuhl: Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU), Prof. Dr.-Ing. Ingrid Verbauwhede (KU Leuven, BE), Prof. Dr.-Ing. Lothar Thiele (ETH Zürich, CH) and Prof. Dr. Tulika Mitra (National University of Singapore, SG) organized and coordinated the Dagstuhl Seminar on "Adaptive Isolation for Predictability and Security".
more information

Appointment to Professorships

Autumn 2016: This year was an outstanding year concerning the professional success of three members of the CRC/Transregio: Prof. Dr.-Ing. Michael Glass (FAU), Dr.-Ing. Muhammad Shafique (KIT) and PD Dr.-Ing. habil. Daniel Lohmann (FAU) were appointed as professors at the highly reputable universities of Ulm, Vienna and Hanover, respectively.

12TH ACM/IEEE Embedded Systems Week (ESWEEK 2016)

Oct. 2-7, 2016, Pittsburgh, USA: Prof. Jörg Henkel (KIT) served as General Chair of the ESWEEK 2016.
more information

Invited Talk, July 29, 2016:
Predictability, Fault Tolerance, and Security on Demand using Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at University of Lübeck, Germany:
The talk gives a short introduction and overview of the topic and benefits of invasive multi-core computing for achieving timing predictability, fault tolerance and security for individual application programs. Here, cores, memory regions and network bandwidth are allocated and freed on demand of each user program for obtaining exclusive usage and access.
It will be shown that through the achieved isolation of resources and thus full applications, the variation of execution time may be reduced drastically for many parallel application programs, i.e., soft real-time image and stream processing. This opens also a way for hybrid performance analysis techniques that combine static timing analysis of applications in isolation and run-time assignment of resources for the execution.
Moreover, the isolation is also beneficial for enabling security on a chip as will be shown. Finally, we present an approach to provide on-demand structural redundancy using invasive computing for a class of massively parallel processor arrays called TCPAs. For protecting safety-critical parallel loop program applications against soft errors, known replication schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) must be lifted to many processors (PEs). Depending on application requirements for reliability and observed Soft Error Rates (SERs), different voting options in hardware and software and analysis techniques for automatic replication scheme selection are presented and compared.

The Munich Workshop on Design Technology Coupling

DTC DTC
June 30-July 1, 2016, Munich: Dr. Helmut Graeb (TU Munich) and Dr. Sani Nassif (Radyalis) organized in cooperation with the DFG Transregional Collaborative Research Center 89 "Invasive Computing" and the SPP 1500 "Dependable Embedded Systems" the "The Munich Workshop on Design Technology Coupling (DTC)". The workshop involved different contributions from industry, e.g., Infineon AG, Bosch GmbH, and Volkswagen AG, as well as from the two DFG-funded research programs. In one session, Prof. Teich gave a short introduction and overview of the topic and benefits of invasive multi-core computing for achieving timing predictability, fault tolerance and security for individual application programs. This talk was followed by the following overviews on providing fault tolerance and power management through invasive computing, "Providing Fault Tolerance Through Invasive Computing" by Dr. Vahid Lari (FAU) and "On-Chip Diagnosis of Multicore Platforms for Power Management" by Mark Sagi (TUM). Furthermore, on 1st of July, the following demonstrations have been presented: An invasive object tracking application that was simulated and visualized in real-time using C2's simulator InvadeSIM, and the code generation for Safe(r) loop computations using the C3's compilation flows.
more information

Special Session at Design Automation Conference (DAC 2016)

June 8, 2016, San Francisco, USA: Prof. Jörg Henkel and Dr.-Ing. Muhammad Shafique (KIT) organised a Special Session on "Cross-Layer Approximate Computing: Challenges and Solutions" at the DAC 2016. more information

Invited Talk, June 6, 2016:
Predictable MPSoC Stream Processing Using Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at University of Texas at Austin, USA:
Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds. Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource (e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time. This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems.
Static solutions to provide the required isolation by allocating distinct resources to safety- or performance-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.
In this talk, we first review and present novel definitions of predictability of execution qualities. Subsequently, we distinguish two techniques for improving predictability called restriction and isolation and present new definitions Then, new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC are introduced based on the paradigm of Invasive Computing. In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In Invasive Computing, isolation is supported on all levels of hardware and software including the OS. Together with restriction (of input uncertainties), the level of on-demand predictability of program execution qualities may be fundamentally increased.
For a broad class of streaming applications, and a concrete demonstration based on a complex object detection application algorithm chain taken from robot vision, we show how jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications. more information

29th GI/ITG International Conference on Architecture of Computing Systems (ARCS)

ARCS 2016 ARCS 2016
April 4-7, 2016, Nuremberg: The 29th International Conference on Architecture of Computing Systems (ARCS 2016) was hosted by the Department of Computer Science at Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany, during April 4–7, 2016. ARCS 2016 took place in Nuremberg at FAU’s Faculty of Business, Economics, and Law in Nuremberg and attracted 100 participants. The conference continued the long-standing ARCS tradition of reporting top-notch results in computer architecture and other related areas. ARCS was founded in 1970 by the German computer pioneer Prof. Wolfgang Händler, who also founded the Computer Science Department at FAU in 1966.
In the welcome address, General Chair Dietmar Fey and Program Chair Frank Hannig, both FAU, highlighted the privilege of having brought ARCS back to its roots in honor of the CS Department’s 50th anniversary and provided statistics on the submissions. In response to the call for papers, 87 submissions were received with affiliations to 31 countries, which clearly demonstrates ARCS’s international character, although a large share (39%) was coming from authors in Germany. With the help of 61 members of the Technical Program Committee, who carried out 325 reviews (about four per submission) and having intensely scrutinized the reviews, we were pleased to present a high-quality technical program that included a total of 29 papers (33%) at the conference.
The strong technical program was complemented by three keynote talks on: "Knights Landing Intel Xeon Phi CPU: Path to Parallelism with General Purpose Programming" by Avinash Sodani, Chief Architect ’Knights Landing’ Xeon-Phi processor at Intel Corporation; "Massive Parallelism – C++ and OpenMP Parallel Programming Models of Today and Tomorrow" by Michael Wong, CEO of OpenMP Corporation; and "Heterogeneous Systems Era" by John Glossner, President of the Heterogeneous System Architecture Foundation (HSAF) and CEO Optimum Semiconductor Technologies; as well as five workshops and a tutorial.
Beside the technical program, the combined visit of the special exhibition "From Abacus to Exascale – Vom Abakus zu Exascale", the conference dinner and best paper award ceremony in the Museum of Industrial Culture in Nuremberg on Wednesday evening was another highlight. ARCS 2016 ARCS 2016



John Glossner and Zoran Salcic visited the TCRC

In the context of ARCS 2016, Dr. John Glossner, President of the Heterogeneous System Architecture Foundation (HSAF) and CEO of Optimum Semiconductor Technologies, and Prof. Zoran Salcic, The University of Auckland, New Zealand, visited also the Transregional Collaborative Research Center Invasive Computing.

John Glossner Zoran Salcic

InvasIC at Hannover Messe 2016

Hannover Messe Hannover Messe
April 25-29, 2016 Hannover, Germany: This year´s Hannover Messe attracted over 190.000 visitors intent on future-proofing their operations and investing in state-of-the-art-technology. At the Research & Technology area Sascha Roloff presented a demonstrator showing the principles of Invasiv Computing.

International Workshop on Multi-Objective Many-Core Design (MOMAC)

Momac Dr. Felix Reimann
April 4/5, 2016, Nuremberg, Germany: Michael Glass and Stefan Wildermann (FAU) organized the Third International Workshop on Multi-Objective Many-Core Design (MOMAC) at the ARCS 2016 at FAU’s Faculty of Business, Economics, and Law in Nuremberg. Dr. Felix Reimann (Audi Electronics Venture GmbH, Gaimersheim, Deutschland) gave a keynote talk on "Towards A Holistic Design Space Exploration for Automotive E/E Architectures".
more information

First Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing

Workshop March 18, 2016, Dresden, Germany: Walter Stechele (TUM), Cristina Silvano (Politecnico di Milano) and Stephan Wong (TU Delft) organized the "First Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing". This Friday-Workshop related to Invasive Computing was collocated at DATE 2016 in Dresden.
more information

Invited Talk, March 18, 2016:
Adaptive Restriction and Isolation for Predictable MPSoC Stream Processing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited keynote talk at First Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing, DATE 2016 in Dresden, Germany:
Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds. Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource (e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time. This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems.
Static solutions to provide the required isolation by allocating distinct resources to safety- or performance-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.
In this invited talk, we first review and present novel definitions of predictability of execution qualities. Subsequently, we distinguish two techniques for improving predictability called restriction and isolation and present new definitions. Then, new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC are introduced based on the paradigm of Invasive Computing. In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In invasive computing, isolation is supported on all levels of hardware and software including the OS. Together with restriction (of input uncertainties), the level of on-demand predictability of program execution qualities may be fundamentally increased.
For a broad class of streaming applications, and a concrete demonstration based on a complex object detection application algorithm chain taken from robot vision, we show how jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications.

Design, Automation and Test in Europe (DATE) 2016

DATE DATE March 14-18, 2016, Dresden: DATE combines the world’s favorite electronic systems design and test conference with an international exhibition for electronic design, automation and test, from system-level hardware and software implementation right down to integrated circuit design. The DATE conference was held at the International Congress Centre Dresden, Germany, from March 14 to 18, 2016.
Out of a total of 829 paper submissions received, a large share (42%) was coming from authors in Europe, 29% of submissions are from Asia, 25% from North America, and 4% from the rest of the world. This clearly demonstrates DATE’s international character, its global reach and impact.
DATE DATE DATE For the 19th successive year, DATE has prepared an exciting technical programme, says Jürgen Teich, Programme Chair of DATE 2016. With the help of 327 members of the Technical Program Committee, who carried out more than 3000 reviews (about four per submission), finally 199 papers (24%) were selected for regular presentation and 81 additional ones (10%) for interactive presentation.
The conference started on Monday with 10 in-depth technical tutorials offered from experts of the industrial and academic worlds on innovative as well as foundational topics related to design solutions, power efficiency, the internet of things, secure systems and testing and diagnosis. In the evening, the well-established PhD Forum allowed selected PhD students from many nationalities to present their PhD thesis work.
As part of the opening ceremony on Tuesday chaired by General Chair Luca Fanucci, University of Pisa and Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, plenary keynote speakers were Luc Van den hove, President and Chief Executive Officer imec talking on “From the happy few to the happy many: towards an intuitive internet of things.”, and Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys talking about “Design will make everything different”. On the same day, the Executive Track offered a series of business panels discussing hot topics. Executive speakers from companies leading the design and automation industry addressed some of the complexity issues in electronics design and discuss about the advanced technology challenge.
The main conference programme from Tuesday to Thursday included 77 technical sessions organized in parallel tracks from the four areas
D – Design Methods and Tools
A – Application Design
T – Test and Robustness
E – Embedded Systems Software
and several special sessions on Hot Topics such as 3D ICs, In-Memory Computing, Heterogeneous Computing, New Transistor for Hardware Security, Embedded Tutorials on Analog-/Mixed Signal Verification Methods and on the Dark Silicon Problem as well as two sessions on selected EU Projects. In addition, the exciting programme of DATE 2016 included a panel on past and future challenges in EDA.
DATE DATE DATE DATE

The conference was complemented by an exhibition which ran for three days (Tuesday – Thursday), offering a comprehensive overview of commercial design and verification tools including vendor seminars and abundant networking possibilities with fringe meetings. This year, there were dedicated campus booths with focus on major trends shaping the future of microelectronics such as IoT and secure systems, Ultra-Low power technologies (FDSOI), 5G wireless networks, 3D-IC integration and automotive systems. Finally, the conference closed on Friday with 8 attractive Friday workshops.

more information

Invited Talk, February 26, 2016:
RaPping and Compilation for Highly Dynamic Parallelism

Prof. Dr.-Ing. Gregor Snelting (IPD, KIT)

Prof. Snelting gave an invited talk at University Saarbrücken, Germany.
PDF

Dagstuhl Seminar 16052 "Dark Silicon: From Embedded to HPC Systems"

Dagstuhl January 31-February 3, 2016, Dagstuhl: Prof. Dr. Gerndt (TUM), Sri Parameswaran (UNSW – Sydney, AU), Barry L. Rountree (LLNL – Livermore, US) and Prof. Dr.-Ing. Glaß (FAU) organizied and coordinated the Dagstuhl Seminar 16052 on "Dark Silicon: From Embedded to HPC Systems":
The goal of this Dagstuhl Seminar is to bring together experts from the different domains and to discuss the state-of-the-art and identify future collaboration topics based on common research interests. We will have three main parts on the topics Dark Silicon, Power and Energy Usage in HPC, and Hybrid Approaches to Resource Management with longer overview presentations by invited speakers and research presentations by the attendees. Each part will close with a discussion slot. After these three parts we plan for group discussion to identify future collaborative research directions.
more information

Invited Keynote Talk, January 19, 2016:
Symbolic Loop Parallelization for Adaptive Multi-Core Systems - Recent Advances and Benefits

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich Prof. Teich gave an invited keynote talk at IMPACT 2016 in Prague, Czech Republic:
With the advent of heterogeneous many-core systems including GPUs and coupled with CPUs and coarse-grain accelerator processor arrays, massively parallel computing on-a-chip is becoming more and more attractive, even for multiple concurrent parallel applications competing dynamically for a certain number and type of processor and memory resources. In this realm, current research initiatives such as Invasive Computing investigate novel solutions how to allocate available resources dynamically between competing applications upon their request to to obtain smallest execution times and achieve high resource utilizations.
In this context, nested loop programs not only form an important source of workload also for the above class of emerging many-core platforms due to their regular computations in polyhedral domains of iterations, but still impose a number of difficult problems to solve in order to adapt a schedule and mapping of a loop nest adaptively to an available region of processors which is not known in size and location until run-time.
In this keynote, symbolic (parametric) loop parallelization techniques are proposed as a remedy to avoid any time- or memory-intensive in-situ compilation on a chip at run-time. Here, some recent results will be summarized how an important class of nested loop programs with parameterized loop bounds may be scheduled and assigned optimally to virtual regions of processors without any need of recompilation at run-time by producing parameterized assembly programs and a proper run-time schedule candidate selection code that initializes the processor codes.
These results may be applied to a multitude of loop nests stemming from numerical benchmarks to signal processing applications to provide predictable and low cost solutions with adaptive speed and ultra-low power consumption. The presented symbolic loop parallelization techniques is applied to a class of massive parallel processor arrays called tightly coupled processor arrays (TCPAs) which allow for non-atomic inter-processor data transfers which are scheduled together with the loop statements. Finally, it is shown that symbolic loop transformations in the polyhedral model not only enable predictable execution time processing for loop nests, but also enable to specify fault-tolerance aspects adaptively. more information

Invited Keynote Talk, January 18, 2016:
The Role of Restriction and Isolation for Increasing the Predictability of MPSoC Stream Processing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited keynote talk at RAPIDO 2016 in Prague, Czech Republic:
Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds.Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource (e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time.This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems.
Static solutions to provide the required isolation by allocating distinct resources to safety-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.
In this keynote, we first review definitions of predictability. We distinguish two techniques for improving predictability called restriction and isolation and present new definitions for predictability. Subsequently, new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC are introduced based on the paradigm of Invasive Computing. In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In invasive computing, isolation is supported on all levels of hardware and software including an invasive OS. Together with restriction (of input uncertainty), the level of on-demand predictability of program execution qualities may be fundamentally increased.
For a broad class of streaming applications, and a particular demonstration based on a complex object detection application algorithm chain taken from robot vision, we show how jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications. more information

Events 2015

Special Session at International Conference on Computer-Aided Design (ICCAD 2015)

November 2, 2015, San Jose, USA: Prof. Jörg Henkel (KIT) organised a Special Session on "Dennard Scaling is History and Moore's Law is Aging: How to break the Inevitable Power Wall??" at the ICCAD 2015. more information

Invasive Computing at the "Lange Nacht der Wissenschaften"

Lange Nacht der Wissenschaften October 24, 2015, Erlangen: Researchers and students of Project C2 vividly demonstrated the principles of Invasive Computing at the Long Night of Sciences ("Lange Nacht der Wissenschaften") in Erlangen. For this purpose, a pan-tilt-zoom camera in form of a Martian was tracking a tennis ball, which could be freely moved by the visitors in the entire room. This object tracking application was simulated and visualized in real-time using C2's simulator InvadeSIM. Hereby, the visitors got fundamental insights into tomorrow's multi-core processor architectures and the concepts of Invasive Computing. more information

DATE 2016 TPC Meeting in Nuremberg, October 29, 2015

Date 2016 TPC Meeting
Programme Chair Prof. Teich hosted the Design Automation and Test in Europe (DATE 2016) TPC Meeting in the Nürnberger Akademie, Nuremberg. More than 200 participants from all over the world attented this meeting to select the technical programme for DATE 2016 that will take place in March 14-18, 2016 in Dresden. Out of a total of 829 paper submissions received, a large share (42%) is coming from authors in Europe, 29% of submissions are from Asia, 25% from North America, and 4% from the rest of the world. This clearly demonstrates DATE’s international character, its global reach and impact. For the 19th successive year DATE has prepared an exciting technical program. With the help of 327 members of the Technical Program Committee who carried out 3062 reviews (about four per submission), finally 199 papers (24%) were selected for regular presentation and 81 additional ones (10%) for interactive presentation.

Special Session at 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2015)

September 30, 2015, Vancouver, Canada: Prof. Jörg Henkel and Dr.-Ing. Muhammad Shafique (KIT) organised a Special Session on "Dark Silicon – From Computation to Communication?" at the NOCS 2015. more information

Invited Keynote Talk, September 24, 2015:
Resource Awareness on Heterogeneous MPSoCs for Image Processing

Prof. Dr.-Ing. Walter Stechele (Integrated Systems, TUM)

Prof. Stechele gave the keynote talk "Resource Awareness on Heterogeneous MPSoCs for Image Processing" at DASIP 2015 in Cracow, Poland.
Multiprocessor System-on-Chip (MPSoC) offers a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, especially with respect to predictability in best effort processing. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to underutilization of some type of PEs while overloading others.
We investigate the benefits of a resource-aware programming model called Invasive Computing for dynamically mapping image processing applications to different types of PEs available on a heterogeneous MPSoC. Results from visual object recognition tasks indicate that resource-aware programming helps to improve the throughput and worst observed latency of the application program along with better overall workload distribution within the heterogeneous MPSoC.
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Siemens Masterpreis 2015

July 30, 2015: Michael Schadhauser (Hardware/Software Co-Design, FAU) received the Siemens Masterpreis 2015 (Siemens Corporate Technology) for his master's thesis "Wissensmanagement in Cyber-Physical Systems mit Techniken des Semantic Web". more information

Special Session at 52nd ACM/EDA/IEEE Design Automation Conference (DAC 2015)

June 11, 2015, San Francisco, USA: Dr.-Ing. Muhammad Shafique (KIT) organised a Special Session on "Dark Silicon: No Way out?" at the DAC 2015. more information

DAC 2015

Sascha Roloff & David Schafhauser

June 7-11, 2015, San Francisco: Sascha Roloff gave a talk about "Execution-Driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures", which was accepted as full paper at the Design Automation Conference (DAC) 2015 in San Francisco. Furthermore, he and the masters student David Schafhauser presented a poster about this paper at the DAC exhibiton area.

ACM SIGDA Outstanding New Faculty Award

Dr.-Ing. Muhammad Shafique June 7-11, 2015, San Francisco: Dr.-Ing. Muhammad Shafique, Research Group Leader at Karlsruhe Institute of Technology (KIT), received the 2015 ACM SIGDA Outstanding New Faculty Award for demonstrating an outstanding potential as a lead researcher and/or educator in the field of electronic design automation.


Invited Talk, June 7, 2015, San Francisco, USA:

Dr.-Ing. Muhammad Shafique (Chair for Embedded Systems, KIT)

Dr.-Ing. Muhammad Shafique gave an invited talk at the Workshop on System-to-Silicon Performance Modeling and Analysis which was part of the 52st ACM/EDA/IEEE Design Automation Conference (DAC 2015). He talked about "Application-Driven Power Management for On-Chip Memories". more information


Invited Keynote Talk, June 02, 2015:
Adaptive Isolation for Predictable MPSoC Stream Processing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave the keynote talk "Adaptive Isolation for Predictable MPSoC Stream Processing" at Scopes 2015 in St. Goar, Germany.
Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds. Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource (e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time. This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems. Static solutions to provide the required isolation by allocating distinct resources to safety-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.
In this keynote, we propose new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC based on the paradigm of Invasive Computing. In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In invasive computing, isolation is supported on all levels of hardware and software including an invasive OS. In case of an abundant number of cores available on an MPSoC today, the problem still becomes how to find suitable claims that will guarantee a performance bound and how to find these, if existing, in a negligible amount of time? For a broad class of streaming applications, we propose a combined static/dynamic approach based on a static design space exploration phase to extract a set of satisfying claim characteristics. For a classe of compositional, but not necessarily homogeneous MPSoC systems, only very little information must then be passed to the OS for run-time claim search in the form of so-called CCGs (claim constraint graphs). We demonstrate the above concepts for a complex object detection application algorithm chain taken from robot vision to show jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications.
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Faszination Technik: "Wieviele Prozessoren passen in eine Hosentasche?"

April 30, 2015, Erlangen: Dr.-Ing. Stefan Wildermann (Hardware/Software Co-Design, FAU) will give a talk on "Wieviele Prozessoren passen in eine Hosentasche?". This event is part of a series of lectures at the Fraunhofer Institut für Integrierte Schaltungen IIS in Erlangen. more information
Abstract: Heutige Chips enthalten nicht einen sondern mehrere Rechenkerne. Anwendungen im Bereich der Signal-, Audio- und Videoverarbeitung profitieren von der hohen Parallelität, wodurch immer mehr „smarte“ Gerätschaften Einzug in unseren Alltag finden. Um die Rechenleistung weiter zu steigern, werden Mikroprozessoren in naher Zukunft sogar hunderte Kerne beinhalten. Doch bereits jetzt befinden sich Milliarden Transistoren auf einem einzigen Chip, die gar nicht gleichzeitig arbeiten können, weil er sonst zu heiß würde. Hier kann nur durch neuartige Techniken ein Zuwachs der Rechenleistung erreicht werden. Daneben müssen Anwendungen sinnvoll programmiert und im Betrieb verwaltet werden, um die verfügbare Parallelität zu nutzen, und auch sicherheitskritische Systeme im Automobil und der Luftfahrt realisieren zu können. Dieser Vortrag stellt aktuelle Trends und Forschungsarbeiten in diesem Themengebiet vor.

International Workshop on Multi-Objective Many-Core Design (MOMAC)

March 24, 2015, Porto, Portugal: Stefan Wildermann and Michael Glass (FAU) organized the Second International Workshop on Multi-Objective Many-Core Design (MOMAC) at the ARCS 2015.
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Keynote Talk, March 24, 2015:
Run-Time Resource and Reliability Management in Dark Silicon Many-Core Chips

Dr.-Ing. Muhammad Shafique (Chair for Embedded Systems, KIT)

Dr. Shafique gave the keynote talk "Run-Time Resource and Reliability Management in Dark Silicon Many-Core Chips" at the Second International Workshop on Multi-Objective Many-Core Design (MOMAC) at the ARCS 2015 in Porto, Portugal.
Due to the technology scaling in the nano-era, the discontinuation of Denard's scaling results in sharp increase in power densities in many-cores that cannot be compensated with cost-efficient cooling mechanisms. Consequently, it leads to the dark silicon problem, where a significant amount of on-chip components in a many-core system cannot be simultaneously powered-on for a given thermal design power (TDP) constraint and stay dark (i.e. power-gated) or at least will be prohibited to operate simultaneously at full speed. Moreover, these high power densities result in high on-chip temperatures that worsen reliability of the many-core systems. The emergence of dark silicon introduces new challenges and opportunities for design and management of many-cores so as to improve quality metrics (performance, reliability, etc.) within peak power and thermal constraints. This talk will provide a short introduction to power-density, temperature, and reliability problems followed by a brief survey of the early explorations on addressing the dark silicon problem. Afterwards, this talk will present novel techniques for efficient resource and reliability management to improve performance and reliability of many-cores under peak power and thermal constraints. more information

Talk, March 18, 2015, New Dehli, India:

Dr.-Ing. Muhammad Shafique (Chair for Embedded Systems, KIT)

Dr.-Ing. Muhammad Shafique gave a talk at the Memory Architecture and Organisation Workshop 2014 which was part of the ESWEEK 2014/ Workshop at CODES+ISSS. He talked about "Application-Driven Power Management for On-Chip Memories". more information


Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) co-located with DATE 2015

Workshop
March 13, 2015, Grenoble, France: Frank Hannig, Dietmar Fey (FAU, Germany) and Anton Lokhmotov (ARM, Cambridge, UK) organised the Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) at the DATE 2015. more information

Workshop: InvasIC meets AVACS, February 11, 2015

This workshop on Predictability and Dependability took place at Parkhotel Schmid in Adelsried.
meeting place

Workshop Workshop Workshop Workshop

IEEE Fellow

January 1, 2015 (effective), Atlanta, USA: Prof. Jörg Henkel (KIT) was appointed IEEE Fellow because of his contributions to hardware/software codesign of embedded computing systems. The award ceremony took place in June 2015.
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Events 2014

Keynote Talk, October 21, 2014:
Dependability of On-Chip Systems in the Dark Silicon Era

Prof. Dr.-Ing. Joerg Henkel (Chair for Embedded Systems, KIT)

Prof. Henkel gave the keynote talk "Dependability of On-Chip Systems in the Dark Silicon Era" at the 32nd IEEE International Conference on Computer Design (ICCD) 2014 in Seoul.
Dependability has become a major design concern as device scaling approaches its limits. Smaller feature sizes lead to higher susceptibility to soft errors, higher process variability and to an accelerated aging of devices. The latter is directly related to temperature, which in fact is responsible for various causes of aging effects like electro migration, NBTI etc. And high on-chip temperature, through high power densities, will enforce to keep some on-chip components idle or at least to prohibit operating them simultaneously at full speed. That is also called “Dark Silicon”. The talk starts by giving an introduction to various reliability jeopardizing effects like aging, the impact temperature has on these and the discontinuation of Dennard Scaling. After presenting the newest research results on the inter-relationship between aging effects, the talk focuses on various techniques to enhance dependability of on-chip systems in the upcoming dark silicon era. more information

Invited Talk, October 16, 2014, New Delhi, India:

Prof. Jürgen Teich (FAU)

Prof. Jürgen Teich gave an invited talk at Multikonferenz Software Engineering & Management 2015 in Dresden. He talked about "Invasives Rechnen" at the special track "Software Engineering in der DFG". more information


Keynote Talk, October 8, 2014:
Invasive Computing - Principles and Benefits

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave the keynote talk "Invasive Computing - Principles and Benefits" at DASIP 2014 in Madrid.
Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present as a new paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs.
The main goal of invasive computing is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects. Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources. The result of an invasion phase is a so-called claim of resources. After termination of a computationally demanding execution phase, the application may release the resources again back to the pool in a phase called retreat. Through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties shall become possible as well.
In the talk, we provide results of the DFG-funded collaborative reseach center TR89 on invasive computing including a) a language definition and implementation for invasive computing based on X10 as developed by IBM. Moreover, we will show how invasive programs may be b) efficiently simulated so to have a testbed for invasive application developers, resource-aware programming, and design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization. Finally, c) a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of video processing algorithm to be executed as a QoS tradeoff with image quality. more information

Invited Talk, September 25, 2014:
System-Level Design Automation of Embedded Systems

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave a talk about "System-Level Design Automation of Embedded Systems" at the meeting of Deutsche Forschungsgesellschaft für Automatisierung und Mikroelektronik e.V. (DFAM). DFAM

Special Session at CODES+ISSS'14, Embedded Systems Week

October 13, 2014, New Delhi, India: Dr.-Ing. Muhammad Shafique (KIT) and Prof. Siddharth Garg (University of Waterloo, Canada) organised a Special Session at CODES+ISSS on "Dark Silicon as a Challenge for Hardware-Software Co-Design". CODES+ISSS 2014 was part of the Embedded Systems Week 2014.
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Best Paper Award at CODES+ISSS 2014

October 15, 2014: Santiago Pagani, Heba Khdr, Waqaas Munawar, Jian-Jia Chen, Muhammad Shafique, Minming Li, and Prof. Jörg Henkel received the Best Paper Award for their contribution "TSP: Thermal Safe Power - Efficient power budgeting for Many-Core Systems in Dark Silicon" in the IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Delhi, India, October 2014. more information


Certificate

DAAD Winter School Tunis, November 26, 2014, Invited Lecture
Coarse-Grained Reconfigurable Architectures - Design and Programming

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich giving a lecture in Tunis

Prof. Teich was invited to give a lecture about "Coarse-Grained Reconfigurable Architectures - Design and Programming" in Tunis, Tunesia. The lecture was part of a winter school on "Design, Programming and Applications of Multi-Processor Systems on Chip". more information

Special Session on "Resource-aware and Domain-specific Computing" at ASILOMAR'14

November 3, 2014, Pacific Grove, USA: Dr.-Ing. Frank Hannig (FAU) organised the Special Session on "Resource-aware and Domain-specific Computing" at the Asilomar Conference on Signals, Systems, and Computers.
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Workshop on "A Roadmap for EDA Research in the Dark Silicon Era" (ICCAD'14)

November 6, 2014, San Jose, USA: Dr.-Ing. Muhammad Shafique (KIT) and Prof. Siddharth Garg (University of Waterloo, Canada) organised a workshop on "A Roadmap for EDA Research in the Dark Silicon Era" as a collocated event at the International Conference on Computer-Aided Design (ICCAD).
This workshop was intended to provide a common platform for EDA experts to discuss their vision and perspectives on the dark silicon problem, and to define a research roadmap for the next decade. This workshop brought together researchers and experts from industry and academia to dwell on whether fundamentally new solutions are required in the context of dark silicon, or conversely, whether existing solutions can be retro-fitted to address these problems. In either scenario, a lively, but informative technical debate is envisioned that will help to carve out a distinct niche for dark silicon research. In keeping with its intent to encourage a diversity of opinions, this workshop will attempt to include speakers in the agenda with alternate perspectives (“dark silicon is just old wine in a new bottle!”).
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24th International Conference on Field Programmable Logic and Applications (FPL 2014)

Prof. Dr. Andreas Herkersdorf (TUM)

September 2-4, 2014, Munich, Germany: The International Conference on Field Programmable Logic and Applications (FPL), organised by Prof. Dr. Andreas Herkersdorf (TUM) is the first and largest conference covering the rapidly growing area of field-programmable logic. During the past 23 years, many of the advances achieved in reconfigurable system architectures, applications, embedded processors, design automation methods (EDA) and tools have been first published in the proceedings of the FPL conference series. Its objective is to bring together researchers and practitioners from both academia and industry from all over the world.

SBBCI 2014 Test of Time Award

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

September 2014, Brasil: Prof. Teich wins the Test of Time Award 2014 of the conference SBCCI (Symposium on Integrated Circuits and Systems Design) for his contribution "Task Scheduling for Heterogeneous Reconfigurable Computers" published in SBCCI 2004. The Test of Time Award 2014 was given to the most cited papers of the SBCCI 2004 edition.

Seminar, July 29, 2014, Montreal:
Foundations and Benefits of Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave a seminar about "Foundations and Benefits of Invasive Computing" at McGill University in Montreal.
McGill University

Invited Talk, June 23, 2014, D.E. Shaw Research, New York:
Automatic Tailoring of System Software: Rethinking the Application–Hardware Bridge

Dr.-Ing. Daniel Lohmann (Computer Science IV, FAU)

System software provides no business value of its own. Its sole purpose is to provide the “right” set of abstractions for the particular application use case: The functional and nonfunctional requirements of the application have to be mapped efficiently to the functional and nonfunctional properties of the hardware. The “ideal” system software does not impair the resulting footprint, robustness, scalability, or predictability by abstractions and policies that do not serve the application’s needs. Between the application and the hardware, the effects of system software should be as “thin” as possible.
In our research, we address this goal by the automatic application--hardware specific tailoring of system software. Platform-specific hardware particularities are not blindly abstracted, but embraced and exploited to offload system services to hardware wherever possible. Our targets reach from automotive hard real-time systems on standard hardware (Sloth) over Linux-based special-purpose systems (VAMOS) to future parallel computing systems based on customized hardware and compiler technology (Invasive Computing). The resulting systems excel with respect to many important nonfunctional properties, including memory footprint, event latency, priority obedience, jitter, and throughput.
» more information Sloth
» more information VAMOS

International Conference on Supercomputing (ICS'14)

June 10-13, 2014 Munich, Germany: Prof. Michael Gerndt (TUM) is co-organiser of the "International Conference on Supercomputing", the premier international forum for the presentation of research results in high-performance computing systems.
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Special Session at 51st ACM/EDA/IEEE Design Automation Conference (DAC 2014)

June 3, 2014, San Francisco, USA: Prof. Jörg Henkel organised a Special Session on "Embedded Resiliency: Approaches for the next Decade" at DAC 2014. more information

DAC 2014 Designer Track Best Poster Award

June 1-5, 2014, San Francisco, USA: Poster "Application-Specific Hierarchical Power Management for Multicast High Efficiency Video Coding", by Muhammad Usman Karim Khan, Muhammad Shafique and Jörg Henkel,at Designer Track, 51st ACM/EDA/IEEE Design Automation Conference (DAC 2014), San Francisco, CA, USA, June 1-5, 2014.
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DAC 2014 Perspective Paper on Dark Silicon

June 1-5, 2014, San Francisco, USA: Titled, "The EDA Challenges in the Dark Silicon Era", on Temperature, Reliability and Variability Perspectives, by Muhammad Shafique, Siddharth Garg, Diana Marculescu and Jörg Henkel, 51st ACM/EDA/IEEE Design Automation Conference (DAC 2014), San Francisco, CA, USA, June 1-5, 2014.

Workshop on Resource awareness and adaptivity in multi-core computing (Racing 2014)

Racing 2014 May 29-30, 2014, Paderborn, Germany: Prof. Dr.-Ing. J. Teich (FAU) and Dr. Frank Hannig (FAU) organised the first Workshop on Resource awareness and adaptivity in multi-core computing (Racing 2014) at the IEEE European Test Symposium (ETS). The steady advances in semiconductor technology allow for increasingly complex SoCs, including multiple (heterogeneous) micro processors, dedicated accelerators, large on-chip memories, sophisticated interconnection networks, and peripherals. However, design, verification, and test as well as parallel programming of such complex multi-core architectures are very challenging since they may have to deal with highly dynamic workloads in different application scenarios and environments. In addition, the architecture might alter itself, either intentionally (e.g., dynamic voltage/frequency scaling, power management) or unintentionally (e.g., failures, aging). As a remedy, one recent research trend in multi-core computing is to design control loops across all platform layers, from application and run-time software down to the status of the underlying hardware. Concepts such as resource-aware programming and adaptive computing are promising candidates for optimizing multi-core systems at run-time with respect to several objectives (utilization, performance, temperature, energy, reliability, dependability, etc.). On the other hand, the enhanced flexibility and adaptivity of such systems raises questions on the predictability of program execution.
The Racing Workshop aims at bringing together researchers and experts from both academia and industry to discuss and exchange research advances from different disciplines in design and test of multi-core architectures as well as programming and run-time management. A distinctive feature of the workshop is its cross section through the entire software/hardware stack, ranging from programming down to multi-core hardware. Thus, Racing is targeted for all of those who are interested in understanding the big picture and the potential of resource-aware and adaptive multi-core computing, its challenges, available solutions, and enables for collaboration of the different domains.
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Invited Talk, May 23, 2014, University of Bologna, Italy:
Foundations and Benefits of Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an Invited Talk in the Seminar Series "Trends in Electronics" at the University of Bologna.

InvasIC is being funded for another term of 4 years!

May 16, 2014: The Grants Committee of the DFG approved the extension of CRC/Transregio 89 for an additional funding period.
short note from May 20, 2014,
press report

Session at HiPEAC Computer Systems Week 2014, Barcelona, Spain:
Dynamic co-optimization of applications and resource management

Keynote Talk, May 13, 2014:
The Dark Silicon Problem in Multi-Core Systems - Invasive Computing as a Solution
Prof. Dr.-Ing. J. Henkel (KIT)

Prof. Henkel Barcelona, Spain, May 2014: As multi-core systems grow more and more complex and at the same time applications’ behavior is less predictable, the so called Dark Silicon problem becomes a severe issue: since Dennard Scaling cannot be sustained any longer, the power density of on-chip multi-core systems reaches levels where not all cores can run at full speed at the same time.
Hence, some cores need to stay “dark” in order meet the thermal design power constraint. Since “dark” cores represent an inefficient way of operating a multi-core system and even question further scaling, sophisticated means for resource management are demanded.
The talk gives an introduction to Invasive Computing, a highly adaptive resource-aware computing paradigm. It is shown that adaptive resource management can indeed alleviate the Dark Silicon problem, allowing operating more cores at a higher speed as to what the thermal design power constraint would allow. The applied resource management techniques are presented and discussed. The talk concludes with some visions on the Dark Silicon problem.

Assisting Run-time Optimization of Many-Core Systems by Design-time Characterization
Prof. Dr.-Ing. M. Glaß (FAU)

Prof. Glass Recent research initiatives target future many-core systems where competing applications can adapt to dynamic usage scenarios and the type and number of available processing elements (PEs). Both the system and the application have functional and extra-functional objectives and constraints. However, the dynamics of the system prohibits static design-time optimization techniques. Instead, the run-time system needs to determine proper implementations of the applications while optimizing system-wide objectives and respecting constraints. We propose rigorous design-time characterization of applications to assist the run-time system by generating implementation variants for applications which are represented as Pareto curves with annotated objectives and architectural requirements and constraints. Based on this information, it is possible to systematically realize run-time systems which can foresee how the selection of implementation variants will influence system-wide objectives and constraints.

Resource Aware Programming with Invasive MPI
I. Compres Urena (TUM)

Hr. Urena Because of the number of cores and hardware threads in modern CPUs, performance today is closely tied to the available parallelism in applications. This parallelism changes at different phases of a program and is typically input dependent. In spite of this, MPI applications today are launched with a fixed number of processes, and lose efficiency as a consequence. Ideally, a program would adjust its used of resources based on the available parallelism at runtime, achieving higher power efficiency and performance. The invasive programming model aims to allow for such resource aware applications. Invasive MPI (iMPI) is a message passing library that is optimized and extended to support the invasive programming model. In this presentation, existing functionality is described and future improvements proposed.

Workshop on Dynamic co-optimization of applications and resource management (HiPEAC Computer Systems Week 2014)

May 13, 2014, Barcelona, Spain: Prof. Dr. Michael Gerndt (TUM) and Dr. Josef Weidendorfer (TUM) organize the first Workshop on Dynamic co-optimization of applications and resource management at HiPEAC Computer Systems Week 2014. Optimal utilization of available resources is a major challenge in the scope of the raising complexity of todays' computer systems consisting of multicore and accelerator components. For best efficiency, both in terms of performance and power consumption, it may be useful to run multiple applications with different resource demands simultaneously, and take their scalability characteristics into account when they compete for available compute and communication capabilities. For best decisions, scheduling algorithms should know about dynamic applications demands and characteristics, and applications may be able to tune their execution if they get notified about scheduling decisions. Such strategies should improve system efficiency in general, but even more so for HPC systems, which currently do not run multiple user jobs simultaneously.
This thematic session wants to bring together research teams and users both from embedded and HPC fields, to discuss different solutions to more efficient resource utilization proposed in various currently running research activities, to trigger new ideas, and to build new connections for upcoming research activities in this context. more information

Inaugural lecture: "Maßschneiderbare Systemsoftware"

April 17, 2014, Erlangen (FAU): Dr.-Ing. Lohmann (FAU) gave his inaugural lecture on "Maßschneiderbare Systemsoftware" at "Tag der Informatik".

Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES)

March 28, 2014, Dresden, Germany: Prof. Dr.-Ing. Stechele from the Technical University of Munich (TUM) organizes a Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES) at the DATE14. The scope of the workshop is to address challenges of embedded portable software development on multi-core structures related to various performance aspects, power efficiency, correctness and reliability including aging. more information

Special Day on System Level Design at DATE 2014

Date 2014 March 26, 2014, Dresden, Germany: Prof. J. Teich, FAU and J. Stahl, Synopsys, Co-Chairs of the DATE 2014.
“The exploitation of recent technology achievements such as more and more processor cores and other IP modules available on a chip today is currently of big interest to many developers in application areas of embedded systems such as automotive, industrial automation and avionics. But there are also very challenging expectations on the achievable improvements and on the available support by tool vendors and system houses to aid handling this increasing system complexity”, says Jürgen Teich, co-chair of the DATE 2014 Special Day on System Level Design. This special day will therefore reflect current industrial practices as well as present recent advances in the System Level Design research area. A particular emphasis will be on ultra-low power design and modeling at multiple abstraction levels, virtual platforms for software development and architecture design of MPSoCs. A panel on “HW/SW Co-Development – The Industrial Workflow” will take place in the afternoon to discuss opportunities and challenges of joint hardware and software development. Moreover, two hot-topic sessions in the morning on “The fight against Dark Silicon” and “Predictable Multi-Core Computing”, and a special session on “System Simulation and Virtual Prototyping” in the afternoon will comprise this special day’s schedule. A particular highlight of the day is the special day´s keynote speech by Dr. Michael Bolle (Executive Vice President Engineering, Bosch), talking about the “Auto cockpit of the future”. more information

International Workshop on Multi-Objective Many-Core Design (MOMAC)

February 25-28, 2014, Luebeck, Germany: Stefan Wildermann and Michael Glass (FAU) are organizing the First International Workshop on Multi-Objective Many-Core Design (MOMAC) at the ARCS 2014.
more information

Session at Embedded World Conference, February 25, 2014, Nuremberg:
Multicore processors for embedded systems: Are we ready?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich participated in this years Embedded World Conference as a speaker on the panel "Multicore processors for embedded systems: Are we ready?" (Session 9). The main focus of the discussion with other multicore experts were the future plans of processor vendors, the challenges of multicore processors in the embedded systems area and important research results that help to face these challenges. » more information.

Events 2013

Keynote Talk, November 25, 2013, MCC13:
Invasive Computing - The Quest for Many-Core Efficiency and Predictability

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Halmstad, Sweden, November 25, 2013: Professor Teich has been invited as a keynote speaker at MCC 13, the 6th Swedish Workshop on Multicore Computing, see » http://www.hh.se/mcc13 in Halmstad, Sweden. He gave an overview of the accomplishments of the Transregional Research Centre Invasive Computing (SFB/TR89) during its first funding phase.

1st International Workshop on Multicore Application Debugging (MAD 2013)

Munich, Germany, November 14-15, 2013: Prof. Dr. Herkersdorf (TUM), Prof. Leupers (RWTH Aachen) and Prof. Chakraborty (TUM) are organizing the First International Workshop on Multicore Application Debugging (MAD 2013) at the TU in Munich . » more information.


Invited Talk, November 11, 2013, University of Exeter, UK:
Parallelisation of dynamically changing grids with a cluster-based approach and invasion

Dipl.-Inf. Martin Schreiber (Informatics V — Scientific Computing, TUM)

Dipl.-Inf. Martin Schreiber gave a talk at the College of Engineering, Mathematics and Physical Sciences (University of Exeter) during his research internship in the UK. » more information.

Invited Talk, November 6, 2013, Imperial College, UK:
Parallelisation of dynamically changing grids with a cluster-based approach and invasion

Dipl.-Inf. Martin Schreiber (Informatics V — Scientific Computing, TUM)

Dipl.-Inf. Martin Schreiber gave an invited talk at the Imperial College (London, UK).
The efficient execution of numerical simulations with dynamical adaptive mesh refinement (DAMR) belongs to one of the major challenges in HPC. With simulations demanding for a steadily changing grid structure, this imposes efficiency requirements on handling that structure as well as managing connectivity and simulation data stored on the grid. Large-scale HPC systems furthermore lead to additional requirements such as load-balancing and thus data migration on distributed-memory systems which are non-trivial for simulations running with DAMR.
The first part of the talk focuses on the optimization and parallelization of DAMR simulations and the second part of the talk is on the optimization of parallelization models currently assigning computational resources statically during program start.

Invited Talk, October 30, 2013, tubs.CITY :
Managing Change and Autonomy for Critical Applications

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at the occasion of the annual Symposium of tubs.CITY, the Center for Informations and Information Theory of the University of Braunschweig, Germany.

Dr.-Ing. Stefan Wildermann is honored with the doctoral award of the STAEDTLER Stiftung.

October 28, 2013: Seit 15 Jahren vergibt die STAEDTLER-Stiftung jährlich 10 Promotionspreise an Doktoranden der Friedrich-Alexander-Universität Erlangen-Nürnberg für außergewöhnliche Leistungen. In diesem Jahr erhält Dr. Stefan Wildermann einen der Promotionspreise der STAEDTLER-Stiftung für seine Doktorarbeit mit dem Titel "Systematic Design of Self-Adaptive Embedded Systems with Applications in Image Processing".
Promotionspreis Dr.-Ing. Stefan Wildermann

Invited Talk, September 30, 2013, ESWEEK, Canada:
The Invasive Computing Paradigm as a Solution for Highly Adaptive and Efficient Multi-core Systems

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich Prof. Teich gave an invited talk at the Special session: "Run-Time Adaptation for Highly-Complex Multi-Core Systems" at ESWEEK in Toronto.
» more information.


Special Session at ESWEEK, September 30, 2013, Montreal, Canada:
Run-Time Adaptation for Highly-Complex Multi-Core Systems

organised by Prof. Henkel (KIT)

ESWEEK 2013 A special session on the topic of "Run-Time Adaptation for Highly-Complex Multi-Core Systems" has been organised by Prof. Jörg Henkel for presentation at ESWEEK in Toronto during the International Conference on Hardware/Software Codesign and System Synthesis (CODESISSS). see » http://esweek.acm.org/codesisss.


Lange Nacht der Wissenschaften 2013 (FAU)

At the Embedded Systems Initiative (ESI) booth at the Science Night 2013, Carolin Böhm-Reichert, Sascha Roloff and Dr. Torsten Klie gave an overview about the current research vision of Invasive Computing, which lets applications demand processors and the computer tries to fulfill them. Under the motto „Friendly Invasion of Processors”, we explained how the workload of several applications can be distributed to more than 100 processors in a fair way.
see »more information.

Lange Nacht der Wissenschaften 2013 Lange Nacht der Wissenschaften 2013

Jürgen Becker ist Ehrendoktor der TWU Budapest

Prof. Dr.-Ing. Dr. h. c. Becker June 2013, TWU Budapest, Hungary: Professor Jürgen Becker, der am Karlsruher Institut für Technologie (KIT) das Institut für Technik der Informationsverarbeitung leitet, hat die Ehrendoktorwürde der Technischen und Wirtschaftswissenschaftlichen Universität (TWU) Budapest erhalten. Die Hochschule zeichnet ihn damit für seine Forschung zu Eingebetteten Systemen aus.


Best Paper Award for InvasIC Team at ASAP13

ASAP13 June 6, 2013, Washington, DC, USA: Prof. Teich (2nd to the right) is honored by receiving the best paper award for the contribution Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays at the 24th IEEE Int. Conference on Application-specific Systems, Architectures and Processors (ASAP13), Washington DC, USA.


Presentation at DAC 2013, June 2-6, 2013, Texas, USA:
Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs

Vahid Lari and Dr. Frank Hannig (Hardware/Software Co-Design, FAU)

DAC 2013 Vahid Lari and Frank Hannig presented in the Designer Track at the 50th Design Automation Conference (DAC) their research on "Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs", a joint work of TCRC 89's projects "B2: Invasive Tightly-Coupled Processor Arrays", "Z2: Validation and Demonstrator", and Synopsys, Inc.
see » http://esweek.acm.org/codesisss.


Tag der Informatik 2013 at the University Erlangen-Nuremberg

April 26, 2013, Erlangen: The focus of this year's "Tag der Informatik" at the FAU is on "Cyber-Physical Systems".
» Program

Invited Talk, April 25, 2013, The 20th annual ASCI Computing Workshop - GNARP 2013 (Leiden, the Netherlands)
Keynote Talk: Invasive Computing - The Quest for Many-Core Efficiency and Predictability

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main goal of "Invasive Computing" is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects. Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources. The result of an invasion phase is a so-called claim of resources. After termination of computational demanding phase, the application may then release the resources again back to the pool in a phase called retreat. Now, through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties becomes possible as well. In the talk, we provide a first language definition and for invasive computing based on X10 as developed by IBM. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization. Finally, a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of the video processing algorithm to be executed as a QoS tradeoff with image quality.

Invited Talk, April 24, 2013, The University of Amsterdam, the Netherlands
More Cores = Less Predictability?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Multi-core technology has become affordable and is offering enourmous opportunities not only with respect to high speed processing data processing, but also for power savings and other objectives.
However, in emerging application domains such as embedded data and reactive processing, maximizing average performance for which these systems have been typically designed for, is not at all the goal. For hard deadline or guaranteed throughput processing, it turns out that available architectures and tools for their programming may introduce a worse predictability than single core systems due to the interference of multiple applications or threads on the same and neighbor cores sharing common resources such as memory, cache, and due to affects resulting from OS service levels such as thread schedulers.
We propose a new paradigm called "invasive computing" and show how to achieve the required predictability for multi-core processing im embedded systems by providing resource isolation on demand. Fundamental changes involve language, compiler, and architecture design.

Invited Talk, April 18, 2013, Innovation Forum Smart Systems, BICCNet:
More Cores = Less Predictability?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

The innovation Forum Smart is organised by the Bavarian Information and Communication Technology Cluster (BICCNet). » more information


Presentation at DATE 2013, March 18-22, 2013, Grenoble, France:
Resource-aware Video Processing on Tightly-Coupled Processor Arrays

Vahid Lari and Dr. Frank Hannig

DATE 2013 Invasive Computing was represented with multiple contributions at DATE 2013. Amongst technical presentations, Vahid Lari (FAU) had a demonstration at DATE'13 University Booth on "Resource-aware Video Processing on Tightly-Coupled Processor Arrays". Here, a prototype of a 5x5 tightly-coupled processor array (TCPA) was demonstrated using a Synopsys CHIPit prototyping platform. The demonstration shows how an invasive image processing application can adapt its quality of image filtering while keeping a fixed level of output throughput (as an application requirement). More specific, an input video stream is fed to the CHIPit system, through a DVI extension board, and processed by the TCPA and then, the output is shown on a display. The targeted applications on the invasive TCPA prototype are several real-time 1-D and 2-D image filters on a streaming input video. Here, based on the number of available PEs in the TCPA, a suitable 2-D edge detection or Gaussian filtering kernel is loaded.
» more information


10th anniversary of Department of Computer Science 12 (Hardware-Software-Co-Design) at FAU

March 8, 2013, FAU: The 10th anniversary of the Department of Computer Science 12 (headed by Prof. Dr.-Ing. Jürgen Teich) will be celebrated on 8th of March 2013. Prof. Franz-Josef Rammig (Heinz Nixdorf Institut, Universität Paderborn) will give the plenary lecture on "Autonomie, Adaptivität, Selbstorganisation: Auf dem Weg zu Cyber Physical Systems".
» Program

Invited Talk, February 24, 2013, "10th Workshop on Optimizations for DSP and Embedded Systems" (Shenzhen, China)
Keynote Talk: Resource-Aware Computing on Domain-Specific Accelerators

Dr.-Ing. Frank Hannig (Hardware/Software Co-Design, FAU)

Talk F. Hannig The continuous progress in semiconductor technology allows for more and more complex processors architectures. The downside of these technological advances is that computing has hit already a power and complexity wall. These days, energy efficiency has become more important than pure computing power. That means, in order to scale computing performance in the future, systems' energy efficiency has to be significantly improved. The design of heterogeneous hardware with different specialized resources, such as accelerators dedicated for one application domain is a promising solution to address this challenge. In this talk, I introduce a class of domain-specific programmable accelerators. In addition, techniques for increasing their energy efficiency as well as resource-aware programming approaches and symbolic mapping techniques for such massively parallel systems are presented.

Invasive Computing News in HPC Wire: "The Week in HPC Research"

February 21, 2013: Invasive Computing has received considerable attention in the HPC community. A contribution by Michael Bader, Hans-Joachim Bungartz, and Martin Schreiber has found mentioning in a news article of HPC Wire under » www.hpcwire.com

Keynote Talk, February 20, 2013, ARCS 2013 (Prague, Czech Republic)
Invasive Computing - The Quest for Many-Core Efficiency and Predictability

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich at ARCS 2013

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main goal of "Invasive Computing" is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects. Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources. The result of an invasion phase is a so-called claim of resources. After termination of computational demanding phase, the application may then release the resources again back to the pool in a phase called retreat. Now, through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties becomes possible as well. In the talk, we provide a first language definition and for invasive computing based on X10 as developed by IBM. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization. Finally, a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of the video processing algorithm to be executed as a QoS tradeoff with image quality.

Dagstuhl-Seminar 13052: Multicore Enablement for Embedded and Cyber Physical Systems, Jan. 27th - Feb. 1st 2013, Schloss Dagstuhl

Prof. Herkersdorf, Prof. Hinchey (University of Limerick) and Prof. Paulitsch (EADS Deutschland)

Participants

Professors Herkersdorf (TUM), Hinchey (University of Limerick) and Paulitsch (EADS Deutschland) are organising the Seminar "Multicore Enablement for Embedded and Cyber Physical Systems" in Schloss Dagstuhl. An Abstract of the Seminar is availabel » here.

Events 2012

Presentation at ReConFig 2012,December 5-7, 2012, Cancun, Mexico:
Adaptive Application-Specific Invasive Microarchitecture demonstrator

Carsten Tradowsky (KIT)

ReConFig2012 Carsten Tradowsky presents an Adaptive Application-Specific Invasive Microarchitecture demonstrator at the 2012 International Conference on ReConFigurable Computing and FPGAs demo night. Additionally, a presentation on the invasive hardware architecture was given.


Workshop at ICCAD, November 8, 2012, San Jose, California:
1st International Workshop on Domain-Specific Multicore Computing

organised by Prof. Teich (FAU) and Prof. Vijay Narayanan (Penn State University)

1st International Workshop on Domain-Specific Multicore Computing Prof. Teich (FAU) and Prof. Vijay Narayanan (Penn State University) are organising the 1st International Workshop on Domain-Specific Multicore Computing at ICCAD 2012. The progam is available as » pdf.



Invited Talk, Friday, October 26, 2012, IBM Böblingen:
Invasive Computing - or - How to Tame 1000+ Cores on a Chip?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main idea of "Invasive Computing" relies on the vision to make application-developers conscious of the temporal computational demands of their programs and that these should be able to spread their load at run-time on processors, communication and memory resources themselves in phases called invasion. First, a language definition and implementation for invasive computing based on X10 as developed by IBM is given. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization.

Invited Talk, Monday, October 15, 2012, HiPEAC Computing Systems Week (Ghent, Belgium):
Models and Assistive Tools for Programming Emerging Architectures

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

At the HiPEAC Computing Systems Week 2012 InvasIC discusses common ties and interdisciplinary cooperation with several EU-funded research projects on models and tools for programming emerging multicore architectures (HiPEAC CSW).

Invited Talk, Friday, September 28, 2012, Paris (UPMC, LIP6):
Invasive Computing: A Systems-Programming Perspective

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Invasive Computing is a research program that aims at developing a new paradigm to address the hardware- and software challenges of managing and using massively-parallel MPSoCs of the years 2020 and beyond. The program encompasses twelve projects from the areas of computer architecture, system software, programming systems, algorithm engineering and applications. The core idea is to let applications manage the available computing resources on a local scope and to provide means for a dynamic and fine-grained expansion and contraction of parallelism. This talk provides a brief overview of the program and presents initial thoughts on system software support for it.

Invited Talk, Thursday, September 20, 2012, Intel Braunschweig:
Prof. Dr.-Ing. Jürgen Teich and Richard Membarth (Hardware/Software Co-Design, FAU)

Prof. Dr.-Ing. Jürgen Teich:
Invasive Computing - or - How to Tame 1000+ Cores on a Chip?

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main idea of "Invasive Computing" relies on the vision to make application-developers conscious of the temporal computational demands of their programs and that these should be able to spread their load at run-time on processors, communication and memory resources themselves in phases called invasion. First, a language definition and implementation for invasive computing based on X10 as developed by IBM is given. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization.

Richard Membarth:
Automatic Code Generation for Image Processing Algorithms on Accelerators in Heterogeneous Architectures

This talk presents the Heterogeneous Image Processing Acceleration (HIPAcc) Framework that allows automatic code generation for algorithms from the domain of medical imaging. By decoupling the algorithm from its schedule in a domain-specific language, efficient code can be generated that leverages the computational power of accelerators such as GPUs. The decoupling allows to map the algorithm to the deep memory hierarchy found in today's GPUs based on domain knowledge and an architecture model of the target machine. Based on the same algorithm description, tailored code variants can be generated for different target architectures, improving programmer productivity significantly.

Special Session at FDL 2012, September 18, 2012, Wien, Austria:
Invasive Programming of Heterogeneous Multi-Core Systems

organised by Christian Haubelt (University of Rostock)

Prof. Jürgen Teich (FAU), Marcel Meyer (TUM) and Prof. Michael Gerndt (TUM) present the Transregio in a Special Session on "Invasive Programming of Heterogeneous Multi-Core Systems" at FDL 2012.

» Program

Invited Talk, Thursday, August 9, 2012, Department of Electrical and Computer Engineering, University of Auckland:
Invasive Computing - or - How to Tame 1000+ Cores on a Chip?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of many concurrent applications can obviously not be organized in a fully centralized way any more as it is done in today’s multi-core processor systems. Also, feature variations are expected to become a severe problem threatening not only performance but also correctness of computations. One way shown how be able to cope with an expected increase of run-time uncertainties is to exploit flexibility of as well the code to be executed as the reconfigurability of the underlying hardware resources. The only major question is at what price this can and should be done, to what degree, and in the control of whom such adaptations shall take place. In this introductory talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main idea of "Invasive Computing" relies on the vision that application-developers are typically conscious of the temporal computational demands of their programs and that these should be able to spread their load at run-time on processors, communication and memory resources themsolves in phases called invasion. Resource-awareness, on the other hand, means that such decisions whether to invade or retreat from resources should be done in reflection with the state of the underlying resources such as temperature-, reliability-, aging-, or fault-monitor information. As an example, spawning more and more threads to an already overloaded MPSoC CPU architecture might lead to less performance than choosing an alternative sequential or approximate computation. In July 2011, the German Research Foundation (DFG) has estalished its transregional collaborative research center TR89 on "Invasive Computing" with Erlangen (FAU), Karlsruhe (KIT) und Munich (TUM) as the three participating research universities with the goal to investigate the paradigm of "Invasive Computing" intensively with respect to the development of new programming and language concepts, architectures of invasible resources, simulation and compiler support as well as application and demonstrator development. Here, we give an overview of the basic principles of "Invasive Computing". In particular, we present a first language definition and implementation for a set of new and not yet existing parallel programming constructs on top of the language X10 as developed by IBM. Also, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, memory organization, etc. It will be finally outlined how and to what degree we may expect invasive computing to improve fault-resilience, scalability, efficiency and resource utilization by the analysis of invasive speedup and efficiency numbers.

Carsten Tradowsky, Florian Thoma, Michael Hübner and Jürgen Becker receive the Best Work-in-Progress Paper Award on the SIES 2012

June 22, 2012: Carsten Tradowsky, Florian Thoma, Michael Hübner and Jürgen Becker receive the Best Work-in-Progress Paper Award for their paper "SPARC: Using an Architrecture Description Language Approach for Modelling an Adaptive Processor Microarchitecture" on the 7th IEE International Symposium on Idustrial Embedded Systems (SIES) 2012.
WIP Paper Award

40th anniversary of Department of Computer Science 4 (Distributed Systems and Operating Systems) at FAU

The 40th anniversary of the Department of Computer Science 4 (headed by Prof. Dr.-Ing. Schröder-Preikschat) will be celebrated on June 29, 2012.
» Program

Prof. Teich visits Dr. Matthias Sauer, Director at Apple, Cupertino, CA.

Jürgen Teich visiting Apple

June 01, 2012: Prof. Teich visits Dr. Matthias Sauer, Director at Apple, Cupertino, CA.­­­

Invited Talk, Fri, May 18, 2012, Hong Kong:
i-Core: Adaptive Computing for Multi-core Architectures

Prof. Dr. Jörg Henkel (CES, KIT)


Tag der Informatik 2012 at the University Erlangen-Nuremberg

April 20, 2012: The focus of this year's "Tag der Informatik" at the FAU is on "Going Parallel – Informatik im Multi-/Many-Core Zeitalter".
» Program

Michael Hübner is apppointed as professor at the Ruhr-Universität Bochum

Since April 2012 Prof. Dr.-Ing. habil. Micha­el Hüb­ner is the Chair for Em­bed­ded Sys­tems for In­for­ma­ti­on Tech­no­lo­gy (ESIT) at the Ruhr-Uni­ver­si­ty of Bo­chum (RUB).

Invited Talk, March 16, 2012, Date 2012 (WS QVVP12), Dresden:
Actor-Based Virtual Prototype Generation

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Abstract—In this talk, we present a solution to generate virtual prototypes from actor-based application models. Generating virtual prototypes from formal application models allows for a two-part design flow: (1) model-specific optimization and automatic design space exploration techniques may be applied to the formal application model; (2) tools and processes established for implementation-oriented virtual prototypes then may be used to achieve to the final implementation. Here, we concentrate on automatic generating a virtual prototype from a formal actor-based application model. Additionally, we highlight an opportunity of such an automatic generation: By sustaining the link between the formal application model and the generated prototype, the formal model may be further exploited in virtual prototype simulation. As a demonstration, we show how this link may be used to accelerate the simulation of an automatically generated SystemC/TLM prototype of a network packet filter by up to 30%.

Invited Talk, Febuary 29, 2012, ARCS 2012 (WS PARMA), Munich:
Introduction to invasive computing and overhead analysis for a shared-memory MPSoC

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

This talk introduces a novel paradigm for the organization of concurrent applications for future many-core systems with thousands or more processing elements called "Invasive Computing". The main idea of this approach is that the application developer is aware of the underlaying resources and reserves these resources explicit with the command invade, distributes the workload with the command infect and frees the resources with the command retreat. The talk also presents an analysis of the performance overheads of invasive computing applications on shared-memory MPSoC architectures. The nature of these is to claim and free resources dynamically at run-time to increase resource efficiency of future MPSoC architectures while not sacrificing speedup in comparison to traditional, statically mapped applications. This holds true especially for programs with highly dynamic parallelism profiles. Based on a formal notation of speedup and resource efficiency for invasive parallel programs, we present a real SPARC LEON-based MPSoC system implementation to evaluate achievable resource efficiencies for realistic workload scenarios showing that the real-measured overhead of invasion can be kept very low and resource efficiencies of up to 100% will become possible without a considerable drop in speedup compared to non-invasive programs using statically allocated resources.

Tamim Asfour is apppointed as professor at the KIT

Since Febuary 2012 Prof. Dr.-Ing. Tamim Asfour­­ is the Chair for Humanoide Robotik Systems at the Karlsruhe Institut ­of Tech­no­lo­gy ­­­­(KIT).

Events 2011

Leibniz-Preis für Peter Sanders

December 08, 2011: Professor Peter Sanders vom Karlsruher Institut für Technologie (KIT) erhält den renommierten Gottfried Wilhelm Leibniz-Preis der Deutschen Forschungsgemeinschaft (DFG) für das Jahr 2012. Der Leibniz-Preis ist mit 2,5 Millionen Euro der international höchstdotierte Wissenschaftspreis. Seit 2004 forscht und lehrt Sanders am KIT. Der Wissenschaftler ist auf internationaler wie auf nationaler Ebene eine der Schlüsselfiguren des Algorithm Engineering.

Mitglieder des SFB/Transregio 89 in DFG-Fachkollegien gewählt

December 08, 2011: Professor Andreas Herkersdorf (TUM) und Professor Jörg Henkel (KIT) wurden in das Fachkollegium "Informatik – Rechnerarchitekturen und eingebettete Systeme" sowie Professor Wolfgang Schröder-Preikschat (FAU) in das Fachkollegium "Informatik – Betriebs-, Kommunikations- und Informationssysteme" der DFG für die Amtsperiode 2012 bis 2015 gewählt.

Invited Talk, November 15, 2011 at TUM:
Frameworks for Multi-core Architectures and GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration

Richard Membarth (FAU) and Wieland Eckert (Siemens Healthcare Sector, Forchheim)

Developing software for multi-core systems and in particular for GPU accelerators imposes major challenges to programmers in medical imaging: in what way should we manage the available resources, divide and distribute the workload, and how can we handle problems arising in parallel processing like race conditions? As a possible remedy, parallelization frameworks have been proposed that relieve the programmer from such low-level tasks. In this talk, we present the evaluation of frameworks for programming multi-core processors and GPU accelerators. Using the 2D/3D image registration as case study, we analyze different aspects of each framework like usability, performance, and parallelization overhead.

Neues Graduiertenkolleg "Heterogene Bildsysteme"

November 14, 2011: Die DFG richtet das neue GRK 1773 an der der Universität Erlangen-Nürnberg ein, in dem heterogene Bildsysteme geplant, entwickelt und realisiert werden sollen. Systeme zur Verarbeitung, Erzeugung und Übertragung digitaler Bilder unterliegen sehr oft hohen Anforderungen mit Blick auf Rechenleistung, Datendurchsatz oder Kosten. Das zeigen etwa Beispiele aus der medizinischen Bildverarbeitung oder Computerspielanwendungen. Die Bildsysteme sind in zweierlei Hinsicht heterogen: Zum einen ist innerhalb eines Systems die Berechnung auf mehrere verschiedenartige Komponenten verteilt, zum anderen gibt es eine große, heterogene Menge an Architekturen, auf denen unterschiedliche Bildanwendungen laufen sollen. Beide Arten von Heterogenität sollen im Graduiertenkolleg erforscht werden. Sprecher des Graduiertenkollegs ist Professor Marc Stamminger. Des Weiteren sind u. a. noch folgende Wissenschaftler, die auch im SFB/Transregio 89 involviert sind, an dem neuen GRK beteiligt: Dr. Frank Hannig, Dr. Daniel Lohmann, Professor Wolfgang Schröder-Preikschat und Professor Jürgen Teich.

Treffen auf der Embedded Systems Week

Jürgen Teich visiting ESWEEK October 10, 2011: Ehemalige (Studenten, Postdocs und Visiting Scholars) von Prof. Edward A. Lee, UC Berkeley, treffen sich auf der Embedded Systems Week (ESWEEK) 2011 in Taipeh, Taiwan.
Prof. Teich verbrachte das Jahr 1994 als Postdoktorand der Deutschen Forschungsgemeinschaft (Visiting Scholar) in der Ptolemy-Forschergruppe von Prof. Lee.


Prof. Teich elected Member of Academia Europaea, the Academy of Europe"

September 24, 2011: Herr Professor Dr.-Ing. Jürgen Teich, Inhaber des Lehrstuhls für Hardware-Software-Co-Design an der Friedrich-Alexander-Universität Erlangen-Nürnberg, wurde zum Mitglied der Academia Europaea (AE), the Academy of Europe, gewählt.
Mitglieder der Academia Europaea sind u. a. führende Wissenschaftler aus den Gebieten Physik, Biologie, Medizin, Mathematik, Literaturwissenschaften, Geisteswissenschaften, Sozialwissenschaften, Kognitionswissenschaften, Wirtschaftswissenschaften und Rechtswissenschaften.
Die Berufung zum Mitglied ist eine große Ehre und Anerkennung für die herausragenden Leistungen von Herrn Professor Teich auf dem Gebiet der Informatik.

Keynote Talk, September 15, 2011 at FAU:
Invasive Parallel Computing - An Introduction

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Jürgen Teich gave a Keynote Talk at the 12th Colloquium of the DFG Priority Programme 1183 "Organic Computing" at FAU.

Invited Talk, September 9, 2011 at Universität zu Lübeck:
Invasive Parallel Computing - An Introduction

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Technology roadmaps foresee already today 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of many concurrent applications can obviously not be organized in a fully centralized way any more as it is done in today's multi-core processor systems. Also, feature variations are expected to become a severe problem threatening not only performance but also correctness of computations. One way shown how be able to cope with an expected increase of run-time uncertainties is to exploit flexibility of as well the code to be executed as the reconfigurability of the underlying hardware resources. The only major question is at what price this can and should be done, to what degree, and in the control of whom such adaptations shall take place. In this introductory talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main idea of "Invasive Computing" relies on the vision that application-developers are typically conscious of the temporal computational demands of their programs and that these should be able to spread their load at run-time on processors, communication and memory resources themsolves in phases called invasion. Resource-awareness, on the other hand, means that such decisions whether to invade or retreat from resources should be done in reflection with the state of the underlying resources such as temperature-, reliability-, aging-, or fault-monitor information. As an example, spawning more and more threads to an already overloaded MPSoC CPU architecture might lead to less performance than choosing an alternative sequential or approximate computation. In July 2011, the German Research Foundation (DFG) has estalished its transregional collaborative research center TR89 on "Invasive Computing" with Erlangen (FAU), Karlsruhe (KIT) und Munich (TUM) as the three participating research universities with the goal to investigate the paradigm of "Invasive Computing" intensively with respect to the development of new programming and language concepts, architectures of invasible resources, simulation and compiler support as well as application and demonstrator development. Here, we give an overview of the basic principles of "Invasive Computing". In particular, we present a first language definition and implementation for a set of new and not yet existing parallel programming constructs on top of the language X10 as developed by IBM. Also, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, memory organization, etc. It will be finally outlined how and to what degree we may expect invasive computing to improve fault-resilience, scalability, efficiency and resource utilization by the analysis of invasive speedup and efficiency numbers.

Prof. Teich wird zum Associate Editor (AE) bestellt"

Prof. Dr.-Ing. Jürgen Teich (Lehrstuhl für Hardware-Software-Co-Design) wird bestellt zum Associate Editor (AE) der Zeitschrift ACM Transactions on Design Automation of Electronic Systems (TODAES), siehe http://todaes.acm.org

Invited Talk, July 25, 2011 at Stanford University (USA):
Invasive Parallel Computing - An Introduction

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Stanford, Gates Building Stanford, Special Seminar Stanford, Teich and Professor Subhasish Mitra
 

Invited Talk, July 22, 2011 at Par Lab, UC Berkeley, USA
Invasive Parallel Computing - An Introduction

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Abstract here
  UC Berkeley UC Berkeley, Teich and Kevin Klues UC Berkeley
 

Events 2010

Invited Talk, October 28, 2010, CASA 2010 at Scottsdale, USA:
Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Invited Talk, August 9, 2010 at The University of Sydney, Australia:
Invasive Computing — An Overview

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Invited Talk, August 6, 2010, National University of Singapore (NUS):
Invasive Computing - A Novel Paradigm for Parallel Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

ASAP 2010 in Rennes (Frankreich)

July 07-09, 2010: Die 21. IEEE International Conference on Application-specific Systems, Architectures and Processors, kurz "ASAP 2010", wurde in diesem Jahr von Prof. Teich mit organisiert.
Ausführliche Informationen zur Konferenz finden Sie auf den Webseiten der ASAP 2010.

Start des DFG Sonderforschungsbereich/Transregio 89

July 01, 2010: Sprecherhochschule ist die Friedrich-Alexander-Universität Erlangen-Nürnberg, Sprecher ist Herr Professor Dr.-Ing. Jürgen Teich. Weitere antragstellende Hochschulen sind das Karlsruher Institut für Technologie und die Technische Universität München.

Begehung

Invited Talk June 13, 2010 at Design Automation Conference (DAC), USA:
Invasive Computing — A Novel Parallel Computing Paradigm

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Invited Talk, April 9, 2010 Frankfurt am Main (30. Sitzung Leitungskreis der Fachgruppe RSS (Rechnergestützter Schaltungs- und Systementwurf), VDE):
Invasives Rechnen

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Verleihung des Humboldt-Forschungspreises an Prof. Dr. Zoran Salcic

March 19, 2010: Im Rahmen der Verleihung des Humboldt-Forschungspreises in Bamberg überreichte Prof. Dr. Helmut Schwarz, Präsident der Alexander-von-Humboldt-Stiftung, heute die Urkunde an Prof. Dr. Zoran Salcic von der University of Auckland, Neu-Seeland. Prof. Salcic ist derzeit Gastprofessor am Lehrstuhl von Prof. Dr.-Ing. Jürgen Teich.

Prof Salcic



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