Publications


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Publication TypeYearAuthor

2018

[1] Andreas Weichslgartner, Stefan Wildermann, Michael Glaß and Jürgen Teich. Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Springer, 2018.

2017

[65] Éricles Sousa, Alexandru Tanase, Frank Hannig and Jürgen Teich. A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE, December 2017. Forthcoming.
[64] Jürgen Teich. Application Mapping Methodologies for NoC-Based MPSoCs. Invited Talk University of California, Irvine, USA, November 14, 2017.
[63] Oliver Reiche, M. Akif Özkan, Richard Membarth, Jürgen Teich and Frank Hannig. Generating FPGA-based Image Processing Accelerators with Hipacc. In Proceedings of the International Conference On Computer Aided Design (ICCAD). IEEE, November 2017. Invited Paper
[62] Sascha Roloff, Frank Hannig and Jürgen Teich. High Performance Network-on-Chip Simulation by Interval-based Timing Predictions. In Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), October 2017. Forthcoming [ DOI ]
[61] Michael Witterauf, Frank Hannig and Jürgen Teich. Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates. In Proceedings of the 28th International Symposium on Rapid System Prototyping (RSP), pages 9–15. ACM, October 2017. [ DOI ]
[60] Alexandru Tanase. Symbolic Parallelization of Nested Loop Programs. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[59] Marcel Brand, Frank Hannig, Alexandru Tanase and Jürgen Teich. Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. In Proceedings of the IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pages 5–12. IEEE Computer Society, September 2017. [ DOI ]
[58] Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel and Jürgen Becker. Auto-SI: An Adaptive Reconfigurable Processor with Run-time Loop Detection and Acceleration. In 30th IEEE International System-on-Chip Conference (SOCC), pages 224–229, September 2017.
[57] Michael Glaß, Jürgen Teich, Martin Lukasiewycz and Felix Reimann. Hybrid Optimization Techniques for System-Level Design Space Exploration. In Handbook of Hardware/Software Codesign, 2017, Springer, pages 217–246. [ DOI ]
[56] Soonhoi Ha, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer and Shuvra S. Bhattacharyya. Introduction to Hardware/Software Codesign. In Handbook of Hardware/Software Codesign, 2017, Springer, pages 3–26. [ DOI ]
[55] Joachim Falk, Christian Haubelt, Jürgen Teich and Christian Zebelein. SysteMoC: A Data-Flow Programming Language for Codesign. In Handbook of Hardware/Software Codesign, 2017, Springer, pages 59–97. [ DOI ]
[54] Santiago Pagani, Muhammad Shafique and Jörg Henkel. Design Space Exploration and Run-Time Adaptation for Multi-Core Resource Management Under Performance and Power Constraints. In Handbook of Hardware/Software Codesign, 2017, Springer, pages 301–332. [ DOI ]
[53] A. Srivatsa, S. Rheindt, T. Wild and A. Herkersdorf. Region Based Cache Coherence for Tiled MPSoCs. In 2017 30th IEEE International System-on-Chip Conference (SOCC), September 2017.
[52] Jürgen Teich. Application Mapping Methodologies for NoC-Based MPSoCs. Invited Talk University Lübeck, September 6, 2017.
[51] Jörg Henkel. The Triangle of Power Density, Circuit Degradation and Reliability. Invited Keynote Speech, 30th IEEE International System-On-Chip Conference (SoCC 2017), Munich, Germany, September 7, 2017.
[50] Johny Paul. Image Processing on Heterogeneous Multiprocessor System-on-Chip using Resource-aware Programming. Dissertation, Technische Universität München, 2017.
[49] Marcel Brand, Frank Hannig, Alexandru Tanase and Jürgen Teich. Efficiency in ILP Processing by Using Orthogonality. In Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 207. IEEE, July 2017. [ DOI ]
[48] Oliver Reiche, Christof Kobylko, Frank Hannig and Jürgen Teich. Auto-Vectorization for Image Processing DSLs. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded systems (LCTES). ACM, June 2017. [ DOI ]
[47] Stephanie Friederich. Automated Hardware Prototyping for 3D Networks on Chips. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), 2017.
[46] E. Glocker, Q. Chen, U. Schlichtmann and D. Schmitt-Landsiedel. Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping. Microprocessors and Microsystems, 50:90-101, May 2017. [ DOI ]
[45] Lukas Meder. Timing Synchronization and Fast-Control for FPGA-based large-scale Readout and Processing Systems. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2017.
[44] Manuel Mohr and Carsten Tradowsky. Pegasus: Efficient Data Transfers for PGAS Languages on Non-Cache-Coherent Many-Cores. In Design, Automation and Test in Europe Conference Exhibition (DATE), pages 1781–1786, March 30, 2017.
[43] Hananeh Aliee. Reliability Analysis and Optimization of Embedded Systems using Stochastic Logic and Importance Measures. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[42] Heba Khdr, Santiago Pagani, Éricles R. Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich and Jörg Henkel. Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Transactions on Computers (TC), 66(3):488–501, March 1, 2017. [ DOI ]
[41] Anuj Pathania, Heba Khdr, Muhammad Shafique, Tulika Mitra and Jörg Henkel. Distributed scheduling for many-cores using cooperative game theory. In Design Automation and Test in Europe (DATE), March 2017.
[40] A. Pathania, V. Venkataramani, M. Shafique, T. Mitra and J. Henkel. Defragmentation of Tasks in Many-Core Architectures. ACM Transactions on Architecture and Code Optimization (TACO), 14(1):2:1–2:21, March 2017. [ DOI ]
[39] Artjom Grudnitsky, Lars Bauer and Jörg Henkel. Efficient Partial Online-Synthesis of Special Instructions for Reconfigurable Processors. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 25(2):594–607, February 2017. [ DOI ]
[38] Andreas Weichslgartner. Application Mapping Methodologies for Invasive NoC-Based Architectures. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[37] Rafael Rosales. Holistic Actor-oriented Modeling of Embedded Systems for ESL Power Consumption Evaluation. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[36] Elisabeth Glocker. Thermisches Verhalten und emuliertes online Temperatur-Monitorsystem für das FPGA-Prototyping von Multiprozessor-Architekturen. Dissertation, Chair of Technical Electronics, Department of Electrical and Computer Engineering, Technical University of Munich, Germany, 2017.
[35] Isañas Alberto Comprés Ureña. Resource-Elasticity Support for Distributed Memory HPC Applications. Dissertation, Technical University of Munich, 2017. [ http ]
[34] Jürgen Teich. Run-Time Monitoring and Enforcement of Non-functional Program Properties of Invasive Programs: Terms and Definitions. Technical Report 01-2017, Hardware/Software Co-Design, Friedrich-Alexander-Universität Erlangen-Nürnberg, Department of Computer Science, 2017.
[33] Marvin Damschen, Lars Bauer and Jörg Henkel. Timing Analysis of Tasks on Runtime Reconfigurable Processors. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 25(1):294–307, January 2017. [ DOI ]
[32] Anatoli Kalysch, Johannes Götzfried and Tilo Müller. VMAttack: Deobfuscating Virtualization-Based Packed Binaries. In Proceedings of the 12th International Conference on Availability, Reliability and Security, pages 2:1–2:10. ACM, 2017. [ DOI ] [ http ]
[31] Job Noorman, Jo Van Bulck, Jan Tobias Mühlberg, Frank Piessens, Pieter Maene, Bart Preneel, Ingrid Verbauwhede, Johannes Götzfried, Tilo Müller and Felix C. Freiling. Sancus 2.0: A Low-Cost Security Architecture for IoT Devices. ACM Trans. Priv. Secur., 20(3):7:1–7:33, 2017. [ DOI ] [ http ]
[30] Pieter Maene, Johannes Götzfried, Ruan de Clercq, Tilo Müller, Felix Freiling and Ingrid Verbauwhede. Hardware-Based Trusted Computing Architectures for Isolation and Attestation. IEEE Transactions on Computers, PP(99):1-1, 2017. [ DOI ]
[29] Alexandru Tanase, Michael Witterauf, Jürgen Teich and Frank Hannig. Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Transactions on Embedded Computing Systems (TECS), 17(2):2017. In press.
[28] Manuel Mohr and Carsten Tradowsky. Pegasus: Efficient Data Transfers for PGAS Languages on Non-Cache-Coherent Many-Cores. In Proceedings of Design, Automation and Test in Europe Conference Exhibition. IEEE, 2017. Forthcoming
[27] Santiago Pagani, Heba Khdr, Jian-Jia Chen, Muhammad Shafique, Minming Li and Jörg Henkel. Thermal Safe Power: Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon. In The Dark Side of Silicon, 2017, Springer,
[26] Santiago Pagani, Heba Khdr, Jian-Jia Chen, Muhammad Shafique, Minming Li and Jörg Henkel. Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon. IEEE Transactions on Computers (TC), 66(1):147-162, 2017. \textbfFeature Paper of the Month [ DOI ]
[25] Santiago Pagani, Anuj Pathania, Muhammad Shafique, Jian-Jia Chen and Jörg Henkel. Energy Efficiency for Clustered Heterogeneous Multicores. IEEE Transactions on Parallel and Distributed Systems (TPDS), 28(5):1315-1330, 2017. [ DOI ]
[24] Christian Dietrich and Daniel Lohmann. OSEK-V: Application-Specific RTOS Instantiation in Hardware. In Proceedings of LCTES '17, 2017. [ DOI ] [ http ]
[23] Christian Dietrich, Peter Wägemann, Peter Ulbrich and Daniel Lohmann. SysWCET: Whole-System Response-Time Analysis for Fixed-Priority Real-Time Systems. In Proceedings of the 23rd Real-Time and Embedded Technology and Applications Symposium (RTAS '17), 2017. Outstanding Paper Award [ DOI ] [ http ]
[22] Christian Dietrich, Valentin Rothberg, Ludwig Füracker, Andreas Ziegler and Daniel Lohmann. cHash: Detection of Redundant Compilations via AST Hashing. In Proceedings of the 2017 USENIX Annual Technical Conference (ATC '17), pages 527–538, 2017. Best Paper Award [ http ]
[21] Ha, Soonhoi and Teich, Jürgen, editors. The Handbook of Hardware/Software Codesign. Springer, 2017. [ DOI ]
[20] Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß and Jürgen Teich. Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems. In Proceedings of the International Conference on Real-Time Networks and Systems (RTNS). IEEE, 2017. Outstanding paper award
[19] Behnaz Pourmohseni, Michael Glaß and Jürgen Teich. Automatic Operating Point Distillation for Hybrid Mapping Methodologies. In Proceedings of Design, Automation and Test in Europe Conference Exhibition (DATE), pages 1135-1140. IEEE, 2017. [ DOI ]
[18] Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker and Andreas Herkersdorf. Efficient Task Spawning for Shared Memory and Message Passing in Many-core Architectures. Journal of Systems Architecture (JSA), 2017. [ DOI ]
[17] Tobias Schwarzer, Andreas Weichslgartner, Michael Glaß, Stefan Wildermann, Peter Brand and Jürgen Teich. Symmetry-eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017. doi: 10.1109/TCAD.2017.2695894 [ DOI ]
[16] Ruan de Clercq, Johannes Götzfried, David Übler, Pieter Maene and Ingrid Verbauwhede. SOFIA: Software and Control Flow Integrity Architecture. Computers & Security, 68:16-35, 2017. [ DOI ]
[15] Johannes Götzfried, Moritz Eckert, Sebastian Schinzel and Tilo Müller. Cache Attacks on Intel SGX. In Proceedings of the Tenth European Workshop on System Security (EuroSec'17), pages 2:1–2:6. ACM, 2017. [ DOI ] [ http ]
[14] Philipp Wagner, Thomas Wild and Andreas Herkersdorf. DiaSys: Improving SoC insight through on-chip diagnosis . Journal of Systems Architecture , 2017. [ DOI ]
[13] Ao Mo-Hellenbrand, Isañas Comprés, Oliver Meister, Hans-Joachim Bungartz, Michael Gerndt and Michael Bader. A Large-Scale Malleable Tsunami Simulation Realized on an Elastic MPI Infrastructure. In Proceedings of the Computing Frontiers Conference (CF), pages 271–274. ACM, 2017. [ DOI ]
[12] Stefan Reif, Timo Hönig and Wolfgang Schröder-Preikschat. In the Heat of Conflict: On the Synchronisation of Critical Sections. In Proceedings of the 20th IEEE Symposium on Real-Time Computing (ISORC 2017), pages 42–51. IEEE Computer Society Press, 2017. [ DOI ]
[11] Volkmar Sieh, Robert Burlacu, Timo Hönig, Heiko Janker, Phillip Raffeck, Peter Wägemann and Wolfgang Schröder-Preikschat. An End-To-End Toolchain: From Automated Cost Modeling to Static WCET and WCEC Analysis. In Proceedings of the 20th IEEE Symposium on Real-Time Computing (ISORC 2017), pages 158–167. IEEE Computer Society Press, 2017. Best paper award [ DOI ]
[10] Peter Wägemann, Tobias Distler, Christian Eichler and Wolfgang Schröder-Preikschat. Benchmark Generation for Timing Analysis. In Proceedings of the 23rd IEEE International Symposium on Real-Time and Embedded Technology and Applications (RTAS '17), pages 319–330. IEEE Computer Society Press, 2017. [ DOI ]
[9] Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi and Ulf Schlichtmann. Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017. accepted for publication
[8] Shushanik Karapetyan and Ulf Schlichtmann. 20nm FinFET-based SRAM Cell: Impact of Variability and Design Choices on Performance Characteristics. In Int. Conf. Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
[7] Mykolai Protsenko. Securing the Android App Ecosystem: Obfuscation, Tamperproofing, and Malware detection. Dissertation, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[6] Simon Schuster, Peter Ulbrich, Isabella Stilkerich, Christian Dietrich and Wolfgang Schröder-Preikschat. Demystifying Soft-Error Mitigation by Control-Flow Checking–-A New Perspective on its Effectiveness. In Proceedings of the 2017 International Conference on Embedded Software (EMSOFT 2017). ACM, 2017. Forthcoming
[5] Alexander Pöppl, Marvin Damschen, Florian Schmaus, Andreas Fried, Manuel Mohr, Matthias Blankertz, Lars Bauer, Jörg Henkel, Wolfgang Schröder-Preikschat and Michael Bader. Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model using Reconfigurable Hardware in Invasive Computing. In Euro-Par 2017: Proceedings of the 10th Workshop on UnConventional High Performance Computing (UCHPC 2017). Springer, 2017.
[4] Ruzena Bajcsy, Yiannis Aloimonos and John K. Tsotsos. Revisiting active perception. Autonomous Robots, :1–20, 2017. [ DOI ]
[3] Markus Grotz, Timothee Habra, Renaud Ronsse and Tamim Asfour. Autonomous View Selection and Gaze Stabilization for Humanoid Robots. In 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)(accepted). IEEE, 2017.
[2] Markus Grotz, Peter Kaiser, Eren Erdal Aksoy, Fabian Paus and Tamim Asfour. Graph-Based Visual Semantic Perception for Humanoid Robots. In 2017 IEEE-RAS 17th International Conference on Humanoid Robots (Humanoids)(accepted). IEEE, 2017.
[1] Timothee Habra, Markus Grotz, David Sippel, Tamim Asfour and Renaud Ronsse. Multimodal Gaze Stabilization of a Humanoid Robot based on Reafferences. In 2017 IEEE-RAS 17th International Conference on Humanoid Robots (Humanoids)(accepted). IEEE, 2017.

2016

[76] Carsten Tradowsky. Methoden zur applikationsspezifischen Effizienzsteigerung adaptiver Prozessorplattformen. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2016.
[75] P. Wagner, L. Li, T. Wild, A. Mayer and A. Herkersdorf. What happens on an MPSoC stays on an MPSoC - unfortunately! In 2016 International Symposium on Integrated Circuits (ISIC), pages 1-2, December 2016. [ DOI ]
[74] Santiago Pagani. Power, Energy, and Thermal Management for Clustered Manycores. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2016. [ DOI ]
[73] Jürgen Teich. Invasive Computing – Editorial. it – Information Technology, 58(6):263–265, November 24, 2016. [ DOI ]
[72] Alexander Pöppl, Michael Bader, Tobias Schwarzer and Michael Glaß. SWE-X10: Simulating shallow water waves with lazy activation of patches using ActorX10. In Proceedings of the 2nd International Workshop on Extreme Scale Programming Models and Middleware (ESPM2), pages 32–39. IEEE, November 2016. [ http ]
[71] Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich and Dibyendu Ghoshal. A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. Journal of Signal Processing Systems, 89(2):225–242, November 1, 2016. [ DOI ]
[70] Vahid Lari, Andreas Weichslgartner, Alex Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jürgen Becker, Jan Heißwolf and Stephanie Friederich. Providing Fault Tolerance Through Invasive Computing. it – Information Technology, 58(6):309–328, October 19 2016. [ DOI ]
[69] Hossein Tajik, Bryan Donyanavard, Nikil Dutt, Janmartin Jahn and Jörg Henkel. SPMPool: Runtime SPM Management for Memory-Intensive Applications in Embedded Many-Cores. ACM Trans. Embed. Comput. Syst., 16(1):25:1–25:27, October 2016. [ DOI ]
[68] Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner and Andreas Zwinkau. Invasive Computing for Timing-Predictable Stream Processing on MPSoCs. it – Information Technology, 58(6):267–280, September 30, 2016. [ DOI ]
[67] Gabor Drescher, Christoph Erhardt, Felix Freiling, Johannes Götzfried, Daniel Lohmann, Pieter Maene, Tilo Müller, Ingrid Verbauwhede, Andreas Weichslgartner and Stefan Wildermann. Providing Security on Demand Using Invasive Computing. it – Information Technology, 58(6):281–295, September 30 2016. [ DOI ]
[66] Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild and Jörg Henkel. Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach. it – Information Technology, 58(6):297–307, September 16, 2016. [ DOI ]
[65] Stephanie Friederich, Marco Neber and Jürgen Becker. Power Management Controller for Online Power Saving in Network-on-Chips. In International Symposium on Embedded Multicore/Manycore SoCs (MCSoC), September 2016.
[64] Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner and Stefan Wildermann. Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution using Invasive Computing. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pages 313-320, September 2016. [ DOI ]
[63] Anas Toma, Santiago Pagani, Jian-Jia Chen, Wolfgang Karl and Jörg Henkel. An Energy-Efficient Middleware for Computation Offloading in Real-Time Embedded Systems. In 22nd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), August 2016.
[62] Jürgen Teich. Predictability, Fault Tolerance, and Security on Demand using Invasive Computing. Invited Talk, University of Lübeck, Germany, July 29, 2016.
[61] Manfred Kröhnert. A Contribution to Resource-Aware Architectures for Humanoid Robots. Dissertation, High Performance Humanoid Technologies (H2T), KIT-Faculty of Informatics, Karlsruhe Institute of Technology (KIT), Germany, 2016.
[60] Michael Witterauf, Alexandru Tanase, Frank Hannig and Jürgen Teich. Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays. In Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 58–66. IEEE, July 2016. [ DOI ]
[59] Jürgen Teich. Invasive Computing - The DFG Transregional Research Center 89. DTC 2016, The Munich Workshop on Design Technology Coupling, Munich, Germany, June 30, 2016.
[58] Vahid Lari. Providing Fault Tolerance Through Invasive Computing. Talk at DTC 2016, The Munich Workshop on Design Technology Coupling, Munich, Germany, June 30, 2016.
[57] Mark Sagi and Andreas Herkersdorf. On-Chip Diagnosis of Multicore Platforms for Power Management. Workshop Presentation, DTC 2016, The Munich Workshop on Design Technology Coupling, Munich, Germany, June 30, 2016.
[56] Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig and Jürgen Teich. ActorX10: An Actor Library for X10. In Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10), pages 24–29. ACM, June 14, 2016. [ DOI ]
[55] Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra and Jörg Henkel. Distributed scheduling for many-cores using cooperative game theory. In Proceedings of the 53rd Annual Design Automation Conference (DAC), pages 133:1–133:6, June 2016.
[54] Ravi Kumar Pujari, Thomas Wild and Andreas Herkersdorf. TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters. In High Performance Computing: 31st International Conference, ISC High Performance 2016, Frankfurt, Germany, June 19-23, 2016, Proceedings, pages 39-58. Springer International Publishing, June 2016. [ DOI ]
[53] Jürgen Teich. Predictable MPSoC Stream Processing Using Invasive Computing. Seminar Talk, Electrical and Computer Engineering, The University of Texas at Austin, USA, June 6, 2016.
[52] Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix Freiling, Michael Glaß and Jürgen Teich. Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 153–162. ACM, May 23, 2016. [ DOI ]
[51] Manfred Kröhnert, Raphael Grimm, Nikolaus Vahrenkamp and Tamim Asfour. Resource-Aware Motion Planning. In IEEE International Conference on Robotics and Automation (ICRA), pages 32–39, May 2016. [ DOI ]
[50] Christopher Eibel, Timo Hönig and Wolfgang Schröder-Preikschat. Energy Claims at Scale: Decreasing the Energy Demand of HPC Workloads at OS Level. In IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pages 1114-1117, May 2016. [ DOI ]
[49] Fazal Hameed, Lars Bauer and Jörg Henkel. Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 35(4):651–664, April 2016.
[48] Jan Heisswolf, Stephanie Friederich, Leonard Masing, Aandreas Weichslgartner, Aurang M. Zaib, Carsten Stein, Marco Duden, Jürgen Teich, Thomas Wild, Andreas Herkersdorf and Jürgen Becker. A Novel NoC-Architecture for Fault Tolerance and Power Saving. In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, April 4, 2016.
[47] Andreas Weichslgartner and Jürgen Teich. Position Paper: Towards Redundant Communication through Hybrid Application Mapping. In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, April 4, 2016.
[46] Jürgen Teich. Adaptive Restriction and Isolation for Predictable MPSoC Stream Procesing. Invited Talk, DATE 2016 Friday Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing, Dresden, Germany, March 18, 2016.
[45] Alexandru Tanase, Michael Witterauf, Éricles R. Sousa, Vahid Lari, Frank Hannig and Jürgen Teich. LoopInvader: A Compiler for Tightly Coupled Processor Arrays. Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March, 2016. [ http ]
[44] Sascha Roloff, Frank Hannig and Jürgen Teich. InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip. Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March, 2016. [ http ]
[43] Jörg Henkel, Santiago Pagani, Heba Khdr, Florian Kriebel, Semeen Rehman and Muhammad Shafique. Towards Performance and Reliability-Efficient Computing in the Dark Silicon Era. In Proceedings of the 19th Design, Automation and Test in Europe (DATE), March 2016.
[42] Shafaq Iqtedar, Osman Hasan, Muhammad Shafique and Jörg Henkel. Formal Probabilistic Analysis of Distributed Resource Management Schemes in On-Chip Systems. In IEEE/ACM 19th Design, Automation and Test in Europe Conference (DATE'16), pages 930–935, March 2016.
[41] Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra and Jörg Henkel. Distributed Fair Scheduling for Many-Cores. In Design Automation and Test in Europe (DATE), pages 379–384, March 2016.
[40] Jürgen Teich. Symbolic Loop Parallelization for Adaptive Multi-Core Systems - Recent Advances and Benefits. Keynote, IMPACT 2016, the 6th International Workshop on Polyhedral Compilation Techniques, 19 January, 2016, Prague, Czech Republic, January 19, 2016.
[39] Jürgen Teich. The Role of Restriction and Isolation for Increasing the Predictability of MPSoC Stream Processing. Keynote, 8th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO 2016), Prague, Czech Republic, January 18, 2016.
[38] Luca Fanucci and Jürgen Teich. Recap of the 2016 DATE Conference & Exhibition. IEEE Design & Test, 33(4):114–117, 2016. [ DOI ]
[37] Sebastian Buchwald, Denis Lohner and Sebastian Ullrich. Verified Construction of Static Single Assignment Form. In 25th International Conference on Compiler Construction, pages 67–76. ACM, 2016. [ DOI ]
[36] Ruan de Clercq, Ronald de Keulenaer, Bart Coppens, Bohan Yang, Pieter Maene, Koen de Bosschere, Bart Preneel, Bjorn de Sutter and Ingrid Verbauwhede. SOFIA: Software and Control Flow Integrity Architecture. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE), pages 1172–1177. IEEE, 2016.
[35] Stephanie Friederich, Niclas Lehmann and Jürgen Becker. Adaptive Bandwidth Router for 3D Network-on-Chips. In Applied Reconfigurable Computing, pages 352–360, 2016. [ DOI ]
[34] Johannes Götzfried, Nico Dörr, Ralph Palutke and Tilo Müller. HyperCrypt: Hypervisor-based Encryption of Kernel and User Space. In 11th International Conference on Availability, Reliability and Security (ARES'16). IEEE, 2016. [ DOI ] [ http ]
[33] Lars Richter, Johannes Götzfried and Tilo Müller. Isolating Operating System Components with Intel SGX. In 1st Workshop on System Software for Trusted Execution (SysTEX'16). ACM, 2016. [ DOI ] [ http ]
[32] Johannes Götzfried, Tilo Müller, Gabor Drescher, Stefan Nürnberger and Michael Backes. RamCrypt: Kernel-based Address Space Encryption for User-mode Processes. In 11th ACM Asia Conference on Computer and Communications Security (ASAICCS). ACM, 2016. [ DOI ] [ http ]
[31] Furkan Turan, Ruan de Clercq, Pieter Maene, Oscar Reparaz and Ingrid Verbauwhede. Hardware Acceleration of a Software-based VPN. In 26th International Conference on Field Programmable Logic and Applications (FPL'16), pages 1-9. IEEE, 2016. [ DOI ]
[30] Hans Michael Gerndt, Michael Glaß, Sri Parameswaran and Barry L. Rountree. Dark Silicon: From Embedded to HPC Systems (Dagstuhl Seminar 16052). Dagstuhl Reports, 6(1):224–244, 2016. [ DOI ]
[29] Weifeng Liu, Michael Gerndt and Bin Gong. Model-based MPI-IO tuning with Periscope tuning framework. Concurrency and Computation: Practice and Experience, 28(1):3–20, 2016. [ DOI ]
[28] David May and Walter Stechele. Voltage over-scaling in sequential circuits for approximate computing. In 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pages 1–6, 2016.
[27] Alexander Pöppl and Alexander Herz. A cache-aware performance prediction framework for GPGPU computations. In Euro-Par 2015: Parallel Processing Workshops. Springer-Verlag, 2016. accepted
[26] Alexander Pöppl and Michael Bader. SWE-X10: An Actor-based and Locally Coordinated Solver for the Shallow Water Equations. In Proceedings of the 6th ACM SIGPLAN Workshop on X10, pages 30–31. ACM, 2016. [ DOI ]
[25] Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang and Bing Li. Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits. In IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pages 705-711. IEEE/ACM Press, January 2016. [ DOI ]
[24] A. K. Singh, M. Shafique, A. Kumar and J. Henkel. Resource and Throughput Aware Execution Trace Analysis for Efficient Run-time Mapping on MPSoCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 35(1):72–85, January 2016. [ DOI ]
[23] Valentin Rothberg, Christian Dietrich, Alexander Graf and Daniel Lohmann. Function Multiverses for Dynamic Variability. In Proceedings of the 2016 IEEE International Workshops on Foundations and Applications of Self* Systems (FAS*W), pages 1–5, 2016. [ DOI ] [ http ]
[22] Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper and Jürgen Becker. A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems. Springer International Publishing, 2016. [ DOI ]
[21] Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper and Jürgen Becker. Adaptive Cache Structures. Springer International Publishing, 2016. [ DOI ]
[20] Carsten Tradowsky, Tanja Harbaum, Leonard Masing and Jürgen Becker. A Novel ADL-based Approach to Design Adaptive Application-Specific Processors. In Best of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016,
[19] Alexander Würstlein, Michael Gernoth, Johannes Götzfried and Tilo Müller. Exzess: Hardware-based RAM Encryption against Physical Memory Disclosure. In Architecture of Computing Systems (ARCS'16). Springer, 2016. [ DOI ] [ http ]
[18] Philipp Wagner, Thomas Wild and Andreas Herkersdorf. DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip. In Architecture of Computing Systems (ARCS'16). Springer, 2016.
[17] Grace Li Zhang, Bing Li and Ulf Schlichtmann. EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers. In Proceedings of the 53rd Annual Design Automation Conference (DAC), pages 60:1–60:6. ACM, 2016. [ DOI ]
[16] Andreas Zwinkau. A Memory Model for X10. In Proceedings of the 6th ACM SIGPLAN Workshop on X10, pages 7–12. ACM, 2016. [ DOI ]
[15] Vahid Lari. Invasive Tightly Coupled Processor Arrays. Springer Singapore, 2016. [ DOI ]
[14] Timo Hönig, Benedict Herzog and Wolfgang Schröder-Preikschat. The Narrow Way: Constructive Measures at Operating-System Level for Low Energy Use. In Proceedings of the 30th Environmental Informatics Conference (EnviroInfo 2016), pages 329-335, 2016.
[13] Mirko Wächter, Simon Ottenhaus, Manfred Kröhnert, Nikolaus Vahrenkamp and Tamim Asfour. The ArmarX Statechart Concept: Graphical Programming of Robot Behaviour. Frontiers in Robotics and AI, 3(33):2016. [ DOI ]
[12] A. Pathania, V. Venkataramani, M. Shafique, T. Mitra and J. Henkel. Optimal Greedy Algorithm for Many-Core Scheduling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), PP(99):1-1, 2016. [ DOI ]
[11] Isañas Comprés, Ao Mo-Hellenbrand, Michael Gerndt and Hans-Joachim Bungartz. Infrastructure and API Extensions for Elastic Execution of MPI Applications. In Proceedings of the 23rd European MPI Users' Group Meeting, pages 82–97. ACM, 2016. [ DOI ]
[10] Oliver Meister, Kaveh Rahnema and Michael Bader. Parallel Memory-Efficient Adaptive Mesh Refinement on Structured Triangular Meshes with Billions of Grid Cells. ACM Transactions on Mathematical Software, 43(3):19:1–19:27, 2016. [ DOI ]
[9] Oliver Meister. Sierpinski Curves for Parallel Adaptive Mesh Refinement in Finite Element and Finite Volume Methods. Dissertation, Technical University of Munich, 2016.
[8] Arash Bakhtiari, Dhairya Malhotra, Amir Raoofy, Miriam Mehl, Hans-Joachim Bungartz and George Biros. A Parallel Arbitrary-Order Accurate AMR Algorithm for the Scalar Advection-Diffusion Equation. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE, 2016.
[7] Gabor Drescher and Wolfgang Schröder-Preikschat. Adaptive Memory Protection for Many-Core Systems. In Adaptive Isolation for Predictability and Security, 2016, Dagstuhl Publishing, pages 120–153:140. [ DOI ] [ http ]
[6] Tulika Mitra, Jürgen Teich and Lothar Thiele. Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441). Dagstuhl Reports, 6(10):120–153, 2016. [ DOI ]
[5] Tigist Abera, N. Asokan, Lucas Davi, Jan-Erik Ekberg, Thomas Nyman, Andrew Paverd, Ahmad-Reza Sadeghi and Gene Tsudik. C-FLAT: Control-Flow Attestation for Embedded Systems Software. In Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, pages 743–754. ACM, 2016.
[4] Michael Gruhn. Forensically Sound Data Acquisition in the Age of Anti-Forensic Innocence. Dissertation, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2016.
[3] Kristof Unterweger. High-performance Coupling of Dynamically Adaptive Grids and Hyperbolic Equation Systems. Dissertation, Technische Universität München, Fakultät für Informatik, 2016.
[2] Mirko Wächter, Simon Ottenhaus, Manfred Kröhnert, Nikolaus Vahrenkamp and Tamim Asfour. The ArmarX Statechart Concept: Graphical Programing of Robot Behavior. Frontiers in Robotics and AI, 3:33, 2016. [ DOI ]
[1] Peter Kaiser, Eren E. Aksoy, Markus Grotz and Tamim Asfour. Towards a Hierarchy of Loco-Manipulation Affordances. In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pages 2839–2846, 2016.

2015

[100] Artjom Grudnitsky. A Reconfigurable Processor for Heterogeneous Multi-Core Architectures. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2015.
[99] Muhammad Usman Karim Khan. Towards Computational Efficiency of Next Generation Multimedia Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2015.
[98] Srinivas Boppu. Code Generation for Tightly Coupled Processor Arrays. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2015.
[97] Santiago Pagani, Jian-Jia Chen, Muhammad Shafique and Jörg Henkel. Thermal-Aware Power Budgeting for Dark Silicon Chips. In Proceedings of the 2nd Workshop on Low-Power Dependable Computing (LPDC) at the International Green and Sustainable Computing Conference (IGSC), December 2015.
[96] Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich and Dietmar Fey. Synthesis and optimization of image processing accelerators using domain knowledge. Journal of Systems Architecture (JSA), December 2015. [ DOI ]
[95] Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann and Jürgen Teich. The Gender Gap in Computer Science –- A Bibliometric Analysis. Technical Report 01-2015, Friedrich-Alexander University Erlangen-Nürnberg, Department of Computer Science, CRC/Transregio 89 Invasive Computing, 2015.
[94] Daniel Lohmann. Configurable System Software. Invited Talk, University of Ulm, November 28, 2015.
[93] Vahid Lari. Invasive Tightly Coupled Processor Arrays. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2015.
[92] Timo Hönig, Christopher Eibel, Benedict Herzog, Heiko Janker, Peter Wägemann and Wolfgang Schröder-Preikschat. Playing Hare and Tortoise: The FigarOS Kernel for Fine-Grained System-Level Energy Optimizations. In 2015 Brazilian Symposium on Computing Systems Engineering (SBESC '15). IEEE, November 2015. [ http ]
[91] Frank Hannig and Andreas Herkersdorf. Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures. Journal of Systems Architecture, 61(10):600, November 7, 2015. [ DOI ]
[90] Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi and Brett H. Meyer. Techniques for On-Demand Structural Redundancy for Massively Parallel Processor Arrays. Journal of Systems Architecture (JSA), 61(10):615–627, November 2015. [ DOI ]
[89] Bing Li and U. Schlichtmann. Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 34(11):1784-1797, November 2015. [ DOI ]
[88] Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles R. Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer and Jörg Henkel. Resource-Awareness on Heterogeneous MPSoCs for Image Processing. Journal of Systems Architecture, 61(10):668–680, November 6, 2015. [ DOI ]
[87] M. Shafique and J. Henkel. Mitigating Power Density and Temperature Problems in the Nano-Era. In IEEE/ACM 34th International Conference on Computer-Aided Design (ICCAD), November 2, 2015. Special Session Paper
[86] Éricles R. Sousa, Frank Hannig and Jürgen Teich. Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. In Proceedings of the International Embedded Systems Symposium (IESS). LNCS, November 2015.
[85] Stefan Wildermann. Time-predictable multi-core programming using Invasive Computing. Invited Talk at ESSEI TecDay: Multicore – The challenge in avionics, October 13, 2015.
[84] Lars Bauer, Artjom Grudnitsky, Marvin Damschen, Srinivas Rao Kerekare and Jörg Henkel. Floating Point Acceleration for Stream Processing Applications in Dynamically Reconfigurable Processors. In IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), October 2015. Invited Paper for the Special Session ``Dynamics and Predictability in Stream Processing – A Contradiction?'' [ DOI ]
[83] Jörg Henkel. Dark Silicon and Dependability. Keynote Talk, International Symposium on Computer Architecture & Digital Systems (CADS), October 8, 2015.
[82] Santiago Pagani, Muhammad Shafique, Heba Khdr, Jian-Jia Chen and Jörg Henkel. seBoost: Selective Boosting for Heterogeneous Manycores. In 10th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 104–113, October 2015. [ DOI ]
[81] R. K. Pujari, T. Wild and A. Herkersdorf. A hardware-based multi-objective thread mapper for tiled manycore architectures. In Computer Design (ICCD), 2015 33rd IEEE International Conference on, pages 459–462, October 2015. [ DOI ]
[80] Sascha Roloff, Stefan Wildermann, Frank Hannig and Jürgen Teich. Invasive Computing for Predictable Stream Processing: A Simulation-based Case Study. In Proceedings of the 13th IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia). IEEE, October 2015. [ DOI ]
[79] Wolfgang Schröder-Preikschat. Predicatbility Issues in Operating Systems. Invited Talk, Technical University Dortmund, October 2, 2015.
[78] Daniel Lohmann. Predictability by Hardware-Centric Operating-System Design. Lecture, Sarntal Akademie, Italy, September 22, 2015.
[77] Wolfgang Schröder-Preikschat. Predicatbility in Operating Systems. Lecture, Sarntal Akademie, Italy, September 22, 2015.
[76] J. Henkel, H. Bukhari, S. Garg, M. U. K. Khan, H. Khdr, F. Kriebel, U. Ogras, S. Parameswaran and M. Shafique. Dark Silicon - From Computation to Communication. In International Symposium on Networks-on-Chip (NOCS), September 2015. Invited Special Session Paper
[75] Daniel Lohmann. Adaptable System Software. Invited Talk, Leibnitz-University Hanover, September 9, 2015.
[74] Santiago Pagani, Jian-Jia Chen and Jörg Henkel. Energy and Peak Power Efficiency Analysis for the Single Voltage Approximation (SVA) Scheme. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 34(9):1415-1428, September 2015. [ DOI ]
[73] Alexandru Tanase, Michael Witterauf, Jürgen Teich and Frank Hannig. Symbolic Loop Parallelization for Balancing I/O and Memory Accesses on Processor Arrays. In Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 188–197. IEEE, September 2015. [ DOI ]
[72] Michael Bader. Performance Optimzation vs. Power - Experiences with Petascale Earthquake Simulations on SuperMUC. Talk at the Workshop on Power-Bounded HPC Performance Optimisation at Schloss Dagstuhl, August, 2015.
[71] Sebastian Buchwald, Manuel Mohr and Ignaz Rutter. Optimal Shuffle Code with Permutation Instructions. In Algorithms and Data Structures, pages 528-541. Springer International Publishing, August 5, 2015. [ DOI ]
[70] Michael Dreschmann, Jan Heisswolf, Michael Geiger, Manuel Haußecker and Jürgen Becker. A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers. In Proceedings of the 28th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 5:1–5:6. ACM, August 2015. [ DOI ]
[69] Moritz Schmid. Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2015.
[68] Andreas Herkersdorf. What happens on an MPSoC stays on an MPSoC \textendash unfortunately! Keynote Talk at MPSoC Forum, July 13, 2015.
[67] Alexander Breuer, Alexander Heinecke, Leonhard Rannabauer and Michael Bader. High-Order ADER-DG Minimizes Energy- and Time-to-Solution of SeisSol. In High Performance Computing, 30th International Conference, ISC High Performance 2015, Frankfurt, Germany, July 12-16, 2015, Proceedings, pages 340–357. Springer, July 2015.
[66] M. U. K. Khan, M. Shafique and J. Henkel. Hierarchical Power Budgeting for Dark Silicon Chips. In ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pages 213–218, July 2015. [ DOI ]
[65] A. Pathania, S. Pagani, M. Shafique and J. Henkel. Power Management for Mobile Games on Asymmetric Multi-Cores. In ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pages 243–248, July 2015. [ DOI ]
[64] Moritz Schmid, Oliver Reiche, Frank Hannig and Jürgen Teich. Loop Coarsening in C-based High-Level Synthesis. In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 166–173. IEEE, July 2015.
[63] Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig and Vahid Lari. On-Demand Fault-Tolerant Loop Processing on Massively Parallel Processor Arrays. In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 194–201. IEEE, July 2015. [ DOI ]
[62] Peter Wägemann, Tobias Distler, Timo Hönig, Heiko Janker, Rüdiger Kapitza and Wolfgang Schröder-Preikschat. Worst-Case Energy Consumption Analyis for Energy-Constrained Embedded Systems. In Proceedings of the 27th EUROMICRO Conference on Real-Time Systems (ECRTS 2015), pages 105–114, July 9, 2015. [ DOI ]
[61] Peter Wägemann, Tobias Distler, Timo Hönig, Volkmar Sieh and Wolfgang Schröder-Preikschat. GenE: A Benchmark Generator for WCET Analysis. In Proceedings of the 15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015), pages 33–43, July 7 2015.
[60] Michael Witterauf, Alexandru Tanase, Frank Hannig and Jürgen Teich. Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing. In Proceedings of the 11th International Summer School on Advanced ComputerArchitecture and Compilation for High-Performance and Embedded Systems (ACACES), pages 205–208, July 2015.
[59] Manuel Mohr, Sebastian Buchwald, Andreas Zwinkau, Christoph Erhardt, Benjamin Oechslein, Jens Schedel and Daniel Lohmann. Cutting Out the Middleman: OS-Level Support for X10 Activities. In Proceedings of the fifth ACM SIGPLAN X10 Workshop, pages 13–18. ACM, June 14, 2015. [ DOI ]
[58] E. Glocker, Q. Chen, A.M. Zaidi, U. Schlichtmann and D. Schmitt-Landsiedel. Emulation of an ASIC power and temperature monitor system for FPGA prototyping. In Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015 10th International Symposium on, pages 1-8, June 2015. [ DOI ]
[57] D. Gnad, M. Shafique, F. Kriebel, S. Rehman, D. Sun and J. Henkel. Hayat: Harnessing Dark Silicon and Variability for Aging Deceleration and Balancing. In 52nd Design Automation Conference (DAC), pages 180:1–180:6, June 2015. \textbfHiPEAC Paper Award [ DOI ]
[56] Timo Hönig. Plan Ahead: Making Energy-Aware Computing Systems. Invited talk, ICSI, Berkeley, CA, USA, June 18, 2015.
[55] Timo Hönig. When Less is More: Invasive Energy Optimizations of System Software. Invited talk, University of California, Berkeley, CA, USA, June 11, 2015.
[54] Timo Hönig, Heiko Janker and Wolfgang Schröder-Preikschat. The FigarOS Operating System Kernel for Fine-Grained System-Level Energy Analysis. In DAC 2015 Workshop on System-to-Silicon Performance Modeling and Analysis: Power, Temperature and Reliability, June 7 2015.
[53] Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klöpfer, Thomas Wild, Andreas Herkersdorf, Jürgen Teich and Jürgen Becker. Fault-tolerant Communication in Invasive Networks on Chip. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pages 1–8. IEEE, June 2015.
[52] J. Henkel, H. Khdr, S. Pagani and M. Shafique. New Trends in Dark Silicon. In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pages 119:1–119:6. ACM, June 2015. \textbfHiPEAC Paper Award [ DOI ]
[51] M. U. K. Khan, M. Shafique and J. Henkel. Hardware-Software Co-Design for Next Generation Dark Silicon Multimedia Systems. Ph.D. Forum at the ACM/EDAC/IEEE 52nd Design Automation Conference (DAC), June, 2015.
[50] H. Khdr, S. Pagani, M. Shafique and J. Henkel. Thermal Constrained Resource Management for Mixed ILP-TLP Workloads in Dark Silicon Chips. In 52nd Design Automation Conference (DAC), pages 179:1–179:6. ACM, June 2015. \textbfHiPEAC Paper Award [ DOI ]
[49] Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig and Brett H. Meyer. A Co-Design Approach for Fault-Tolerant Loop Execution on Coarse-Grained Reconfigurable Arrays. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pages 1–8. IEEE, June 2015. [ DOI ]
[48] Santiago Pagani, Muhammad Shafique, Jian-Jia Chen and Jörg Henkel. Thermal-Aware Power Budgeting for Dark Silicon Chips (Invited talk). In Workshop on System-to-Silicon Performance Modeling and Analysis at the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), June 2015.
[47] Sascha Roloff, David Schafhauser, Frank Hannig and Jürgen Teich. Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures. In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pages 44:1–44:6. ACM, June 2015. [ DOI ]
[46] Éricles R. Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen and Ulf Schlichtmann. Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 121–124. ACM, June 2015. [ DOI ]
[45] Jürgen Teich. Adaptive Isolation for Predictable MPSoC Stream Processing. Keynote, SCOPES 2015, 18th International Workshop on Software and Compilers for Embedded Systems, Schloss Rheinfels, St. Goar, Germany, June 2, 2015.
[44] Jürgen Teich. Adaptive Isolation for Predictable MPSoC Stream Processing. In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2015), pages 1-2, June 2015. [ DOI ]
[43] Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau and Gregor Snelting. Adaptive Fault Tolerance through Invasive Computing. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pages 1–8. IEEE, June 2015. [ DOI ]
[42] Sebastian Kobbe. Scalable and Distributed Resource Management for Many-Core Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2015.
[41] Jörg Henkel, Muhammad Usman Karim Khan and Muhammad Shafique. Energy-Efficient Multimedia Systems for High Efficiency Video Coding. In IEEE International Symposium on Circuits and Systems (ISCAS), May 2015. (accepted as a reviewed Special Session paper)
[40] Janmartin Jahn, Santiago Pagani, Sebastian Kobbe, Jian-Jia Chen and Jörg Henkel. Runtime Resource Allocation for Software Pipelines. ACM Transactions on Parallel Computing (TOPC), 2(1):5:1–5:23, May 2015. [ DOI ]
[39] Philipp Wagner, Lin Li, Thomas Wild, Albrecht Mayer and Andreas Herkersdorf. Knowledge-Based On-Chip Diagnosis for Multi-Core Systems-on-Chip. In edaWorkshop 15, pages 39–45, May 2015.
[38] Stefan Wildermann, Andreas Weichslgartner and Jürgen Teich. Design Methodology and Run-time Management for Predictable Many-Core Systems. In Proceedings of the 6th IEEE Workshop on Self-Organizing Real-Time Systems (SORT), pages 1–8, April 13 2015.
[37] Wolfgang Schröder-Preikschat. Invasive Computing: A Systems-Programming Perspective. Invited talk, Auckland University, Auckland, New Zealand, April 10, 2015.
[36] Sebastian Buchwald. Optgen: A Generator for Local Optimizations. In Proceedings of the International Conference on Compiler Construction (CC), pages 171–189. Springer Berlin Heidelberg, April 18, 2015. [ DOI ]
[35] Gabor Drescher and Wolfgang Schröder-Preikschat. Guarded Sections: Structuring Aid for Wait-Free Synchronisation. Poster at the 18th IEEE Symposium on Real-Time Computing (ISORC 2015). April 15, 2015.
[34] Preethi Parayil, Aurang Zaib, Thomas Wild, Stefan Wallentowitz and Andreas Herkersdorf. Sharer Status-based Caching in tiled Multiprocessor Systems-on-Chip. In HPC 2015 – 23rd High Performance Computing Symposia, pages 67–74. SCS, The Society for Modeling & Simulation, April 2015.
[33] Jürgen Teich, Srinivas Boppu, Frank Hannig and Vahid Lari. Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays. In Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung, 2015, Imperial College Press, pages 167–206. [ DOI ]
[32] Stefan Wildermann. Wieviele Prozessoren passen in eine Hosentasche? Invited Talk at Öffentliche Vortragsreihe Faszination Technik, April, 2015.
[31] Jürgen Teich. Invasive Computing. Invited Talk, SE 2015, Software Engineering and Management, Special Session Software Engineering in der DFG, Dresden, Germany, March 19, 2015.
[30] Michael Bader. Vectorization of Riemann Solvers for the Shallow Water Equations. Minisymposium Flooding the Cores - Computing Flooding Events with Many-Core and Accelerator Technologies at SIAM Conference on Computational Science and Engineering, March, 2015.
[29] Sebastian Buchwald, Manuel Mohr and Andreas Zwinkau. Malleable Invasive Applications. In Proceedings of the 8th Working Conference on Programming Languages (ATPS). Springer Berlin Heidelberg, March 18 2015.
[28] M. U. K. Khan, M. Shafique and J. Henkel. Hardware-Software Co-Design for Next Generation Dark Silicon Multimedia Systems. Ph.D. Forum at the IEEE/ACM 16th Design Automation and Test in Europe Conference (DATE). Ph.D. Forum Best Poster Award, March, 2015.
[27] Sebastian Kobbe, Lars Bauer and Jörg Henkel. Adaptive on-the-fly Application Performance Modeling for Many Cores. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 730–735, March 2015.
[26] Santiago Pagani, Jian-Jia Chen, Muhammad Shafique and Jörg Henkel. MatEx: Efficient Transient and Peak Temperature Computation for Compact Thermal Models. In 18th Design, Automation and Test in Europe (DATE), pages 1515–1520, March 2015. [ DOI ]
[25] Muhammad Shafique. Run-Time Resource and Reliability Management in Dark Silicon Many-Core Chips. Keynote Talk, International Workshop on Multi-Objective Many-Core Design (MOMAC), March, 2015.
[24] Muhammad Shafique, Dennis Gnad, Siddharth Garg and Jörg Henkel. Variability-Aware Dark Silicon Management in On-Chip Many-Core Systems. In 18th IEEE/ACM Design, Automation and Test in Europe (DATE), March 2015.
[23] Andreas Weichslgartner, Jan Heisswolf, Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jürgen Becker and Jürgen Teich. Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures. In Proceedings of the second International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, March 2015.
[22] C. Diniz, M. Shafique, S. Bampi and J. Henkel. A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 34(2):February 2015.
[21] Fazal Hameed. DRAM aware Last-Level-Cache policies for Multi-core Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2015.
[20] Daniel Lohmann. Two-Dimensional Tailoring of RTOS Kernels: Rethinking the Hardware–Application Bridge. Invited Talk, INRIA/LIP6 Paris, January 15, 2015.
[19] Maxim Anikeev, Felix Freiling, Johannes Götzfried and Tilo Müller. Secure garbage collection: Preventing malicious data harvesting from deallocated Java objects inside the Dalvik VM. In Journal of Information Security and Applications, pages 81–86. Elsevier, 2015. [ DOI ]
[18] Ruan De Clercq, Sujoy Sinha Roy, Ingrid Verbauwhede and Frederik Vercauteren. Efficient Software Implementation of Ring-LWE Encryption. In Design, Automation and Test in Europe (DATE 2015). IEEE, 2015.
[17] Gabor Drescher and Wolfgang Schröder-Preikschat. An Experiment in Wait-Free Synchronisation of Priority-Controlled Simultaneous Processes: Guarded Sections. Technical Report CS-2015-01, Friedrich-Alexander-Universität Erlangen-Nürnberg, Department of Computer Science, 2015.
[16] Gabor Drescher and Wolfgang Schröder-Preikschat. Wartefreie Synchronisation von Echtzeitprozessen mittels abgeschirmter Abschnitte. In Echtzeit 2015 –- Betriebssysteme und Echtzeit, pages 59–68. Springer, 2015.
[15] Gabor Drescher and Wolfgang Schröder-Preikschat. Guarded Sections: Structuring Aid for Wait-Free Synchronisation. In Proceedings of the 18th IEEE Symposium on Real-Time Computing (ISORC 2015), pages 280–283. IEEE Computer Society Press, 2015.
[14] Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris and Jürgen Becker. A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. In Applied Reconfigurable Computing, 2015, Springer International Publishing, pages 311-320.
[13] Johannes Götzfried, Tilo Müller, Ruan de Clercq, Pieter Maene, Felix Freiling and Ingrid Verbauwhede. Soteria: Offline Software Protection within Low-cost Embedded Devices. In Proceedings of the 31th Annual Computer Security Applications Conference (ACSAC'15), pages 241–250. ACM, 2015. [ DOI ] [ http ]
[12] Dennis Giffhorn and Gregor Snelting. A New Algorithm for Low-Deterministic Security. International Journal of Information Security, 14(3):263–287, 2015. [ DOI ]
[11] Christopher Kugler and Tilo Müller. Separated Control and Data Stacks to Mitigate Buffer Overflow Exploits. In Endorsed Transactions on Security and Safety, pages 1–36. European Alliance for Innovation (EAI), Institute for Computer Sciences, Social Informatics and Telecommunications Engineering (ICST), 2015.
[10] Andreas Lankes. A Selective Packet Discard Technique for Efficient Deadlock Recovery in Networks-on-Chip. Dissertation, Technische Universität München, Fakultät für Elektrotechnik und Informationstechnik, 2015.
[9] David May and Walter Stechele. Design of fine-grained sequential approximate circuits using probability-aware fault emulation. In Low Power Electronics and Design (ISLPED), 2015 IEEE/ACM International Symposium on, pages 73–78, 2015.
[8] Pieter Maene and Ingrid Verbauwhede. Single-Cycle Implementations of Block Ciphers. In Lightweight Cryptography for Security and Privacy. Springer-Verlag, 2015.
[7] Johny Paul, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Manfred Kröhnert, Daniel Lohmann, Walter Stechele, Tamim Asfour and Wolfgang Schröder-Preikschat. Self-adaptive corner detection on mpsoc through resource-aware programming. Journal of Systems Architecture, 2015. [ DOI ]
[6] Maximilian Seitzer, Michael Gruhn and Tilo Müller. A Bytecode Interpreter for Secure Program Execution in Untrusted Main Memory. In 20th European Symposium on Research in Computer Security (ESORICS'15), pages 376–395. SBA Research, 2015.
[5] Gregor Snelting. Understanding Probabilistic Software Leaks. Science of Computer Programming, 97, Part 1(0):122-126, January 2015. Special Issue on New Ideas and Emerging Results in Understanding Software [ DOI ]
[4] N. Vahrenkamp, M. Wächter, M. Kröhnert, K. Welke and T. Asfour. The Robot Software Framework ArmarX. Information Technology, 57(2):99–111, 2015.
[3] Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker and Andreas Herkersdorf. Network Interface with Task Spawning Support for NoC-based DSM Architectures. In 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS), pages 186–198. Springer, 2015. [ DOI ]
[2] Oliver Meister and Michael Bader. 2D adaptivity for 3D problems: Parallel SPE10 reservoir simulation on dynamically adaptive prism grids. Journal of Computational Science, 9:101–106, 2015. Special Issue ICCS 2015
[1] Peter Kaiser, Markus Grotz, Eren E. Aksoy, Martin Do, Nikolaus Vahrenkamp and Tamim Asfour. Validation of Whole-Body Loco-Manipulation Affordances for Pushability and Liftability. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 920–927, 2015.

2014

[96] Waqaas Munawar, Heba Khdr, Santiago Pagani, Muhammad Shafique, Jian-Jia Chen and Jörg Henkel. Peak Power Management for Scheduling Real-time Tasks on Heterogeneous Many-Core Systems. In 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS), December 2014.
[95] Christoph Roth. Parallele und kooperative Simulation für eingebettete Multiprozessorsysteme. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), 2014. [ http ]
[94] M. Shafique and S. Rehman. Designing and Architecting Advanced Embedded Systems. Tutorial at National University of Sciences and Technology (NUST), December, 2014.
[93] Jürgen Teich. Reconfigurable Computing for MPSoC. Invited Lecture, Winter School Design and Applications of Multi Processor System on Chip, Tunis, Tunesia, November 26, 2014.
[92] Jan Heisswolf. A Scalable and Adaptive Network on Chip for Many-Core Architectures. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), 2014. [ http ]
[91] Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig and Jürgen Teich. Application-driven Reconfiguration of Shared Resources for Timing Predictability of MPSoC Platforms. In Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), pages 398–403. IEEE, November 2014. [ DOI ]
[90] Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi and Jörg Henkel. Energy-Efficient Architecture for Advanced Video Memory. In IEEE/ACM 33rd International Conference on Computer-Aided Design (ICCAD), November 2014.
[89] Wolfgang Schröder-Preikschat. Invasive Computing: A Systems-Programming Perspective. Invited talk, TU Dresden, Institute of Systems Architecture, November 7, 2014.
[88] Muhammad Shafique. Application-Driven Power Management for On-Chip Memories. Invited Talk at Memory Architecture and Organization Workshop (MeAOW) at ESWeek, October 16,, 2014.
[87] Sebastian Graf, Felix Reimann, Michael Glaß and Jürgen Teich. Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded System Design and Optimization. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), pages 2:1–2:10, October 12, 2014. [ DOI ]
[86] Artjom Grudnitsky, Lars Bauer and Jörg Henkel. COREFAB: Concurrent Reconfigurable Fabric Utilization in Heterogeneous Multi-Core Systems. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2014. [ DOI ]
[85] Timo Hönig, Heiko Janker, Oliver Mihelic, Christopher Eibel, Rüdiger Kapitza and Wolfgang Schröder-Preikschat. Proactive Energy-Aware Programming with PEEK. In 2014 Conference on Timely Results in Operating Systems (TRIOS '14). USENIX Association, October 2014. [ http ]
[84] Martin Haaß, Lars Bauer and Jörg Henkel. Automatic Custom Instruction Identification in Memory Streaming Algorithms. In International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2014. [ DOI ]
[83] Jörg Henkel. Dependability of On-Chip Systems in the Dark Silicon Era. Keynote Talk, 32nd IEEE International Conference on Computer Design (ICCD), October, 2014.
[82] Jörg Henkel, Lars Bauer, Artjom Grudnitsky and Hongyan Zhang. Adaptive Embedded Computing with i-Core. In ACM SIGBED Review – Special Issue on the 6th Workshop on Adaptive and Reconfigurable Embedded Systems, pages 20–21, October 2014. Extended Abstract for Keynote Talk [ DOI ]
[81] Santiago Pagani, Heba Khdr, Waqaas Munawar, Jian-Jia Chen, Muhammad Shafique, Minming Li and Jörg Henkel. TSP: Thermal Safe Power - Efficient power budgeting for Many-Core Systems in Dark Silicon. In 9th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 10:1–10:10, October 2014. \textbfBest Paper Award [ DOI ]
[80] Johny Paul, Walter Stechele, Éricles R. Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert and Tamim Asfour. Self-Adaptive Harris Corner Detector on Heterogeneous Many-Core Processor. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP). IEEE, October 2014. [ DOI ]
[79] Muhammad Shafique, Siddharth Garg, Tulika Mitra, Sri Parameswaran and Jörg Henkel. Dark Silicon As a Challenge for Hardware/Software Co-design: Invited Special Session Paper. In IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2014. [ DOI ]
[78] Muhammad Shafique, Muhammad Usman Karim Khan and Jörg Henkel. Power Efficient and Workload Balanced Tiling for Parallelized High Efficiency Video Coding. In 21st IEEE International Conference on Image Processing (ICIP), October 2014.
[77] Isabella Stilkerich, Michael Strotz, Christoph Erhardt and Michael Stilkerich. RT-LAGC: Fragmentation-Tolerant Real-Time Memory Management Revisited. In Proceedings of the 12th International Workshop on Java Technologies for Real-time and Embedded Systems (JTRES '14), pages 87–96. ACM, October 14, 2014. [ DOI ]
[76] Isabella Stilkerich, Philip Taffner, Christoph Erhardt, Christian Dietrich, Christian Wawersich and Michael Stilkerich. Team Up: Cooperative Memory Management in Embedded Systems. In Proceedings of the 2014 Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES'14), pages Art. No. 10. ACM, October 13, 2014. [ DOI ]
[75] Alexandru Tanase, Michael Witterauf, Jürgen Teich and Frank Hannig. Symbolic Inner Loop Parallelisation for Massively Parallel Processor Arrays. In Proceedings of the 12th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 219–228, October 2014. [ DOI ]
[74] Jürgen Teich. Invasive Computing – Concepts and Benefits. Keynote, DASIP 2014, Conference on Design and Architectures for Signal and Image Processing, Madrid, Spain, October 8, 2014.
[73] Peter Wägemann, Timo Hönig, Rüdiger Kapitza and Wolfgang Schröder-Preikschat. Worst-Case Energy Consumption Analysis for Soft and Hard Energy Systems. 11th USENIX Symposium on Operating System Design and Implementation (OSDI '14) October 2014. Poster.
[72] Andreas Weichslgartner, Deepak Gangadharan, Stefan Wildermann, Michael Glaß and Jürgen Teich. DAARM: Design-Time Application Analysis and Run-Time Mapping for Predictable Execution in Many-Core Systems. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), pages 1–10, October 2014. [ DOI ]
[71] Jürgen Teich. System-Level Design Automation of Embedded Systems. Invited Talk, Tagung Deutsche Forschungsgesellschaft für Automatisierung und Mikroelektronik e.V. (DFAM), September 25, 2014.
[70] Stephanie Friederich, Jan Heisswolf and Jürgen Becker. Hardware/software debugging of large scale many-core architectures. In Proceedings of the 27th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1–7. IEEE, September 2014. [ DOI ]
[69] Martin Schreiber, Christoph Riesinger, Tobias Neckel, Hans-Joachim Bungartz and Alexander Breuer. Invasive Compute Balancing for Applications with Shared and Hybrid Parallelization. International Journal of Parallel Programming, September 2014. [ DOI ]
[68] Tobias Weinzierl, Michael Bader, Kristof Unterweger and Roland Wittmann. Block Fusion on Dynamically Adaptive Spacetree Grids for Shallow Water Waves. Parallel Processing Letters, 24(3):1441006, September 2014.
[67] Stefan Nürnberger, Gabor Drescher, Randolf Rotta, Jörg Nolte and Wolfgang Schröder-Preikschat. Shared Memory in the Many-Core Age. In Proceedings of the International Workshop on Runtime and Operating Systems for the Many-core Era (ROME 2014). Springer, August 26, 2014.
[66] Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi and Jörg Henkel. Content-Driven Memory Pressure Balancing and Video Memory Power Management for Parallel High Efficiency Video Coding. In ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2014. [ DOI ]
[65] Éricles Sousa, Deepak Gangadharan, Frank Hannig and Jürgen Teich. Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. In Proceedings of the EUROMICRO Digital System Design Conference (DSD), pages 74–81. IEEE, August 2014. [ DOI ]
[64] Jürgen Teich. Foundations and Benefits of Invasive Computing. Seminar, Mc Gill University, Montreal, July 29, 2014.
[63] Jürgen Teich, Alexandru Tanase and Frank Hannig. Symbolic Mapping of Loop Programs onto Processor Arrays. Journal of Signal Processing Systems, 77(1–2):31–59, July 11, 2014. [ DOI ]
[62] Daniel Lohmann. Automatic Tailoring of System Software: Rethinking the Application-Hardware Bridge. Invited talk June 23, 2014. D. E. Shaw Research, New York City, USA.
[61] R. de Clercq, F. Piessens, D. Schellekens and I. Verbauwhede. Secure Interrupts on Low-End Microcontrollers. In IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 147–152, June 2014. [ DOI ]
[60] Fazal Hameed, Lars Bauer and Jörg Henkel. Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. In IEEE/ACM Design Automation Conference (DAC), June 2014. [ DOI ]
[59] M. U. K. Khan, M. Shafique and J. Henkel. Application-Specific Hierarchical Power Management for Multicast High Efficiency Video Coding. In ACM/EDAC/IEEE 51st Design Automation Conference (DAC), June 2014. Designer Track Best Poster Award
[58] Muhammad Shafique, Siddharth Garg, Jörg Henkel and Diana Marculescu. The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives. In 51st Design Automation Conference (DAC), June 2014. [ DOI ]
[57] Srinivas Boppu, Frank Hannig and Jürgen Teich. Compact Code Generation for Tightly-Coupled Processor Arrays. Journal of Signal Processing Systems, 77(1–2):5–29, May 31, 2014. [ DOI ]
[56] Jürgen Teich. Introduction to Invasive Computing. Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), Paderborn, Germany, Tutorial Talk, May 29, 2014.
[55] Jürgen Teich. Foundations and Benefits of Invasive Computing. University of Bologna, Italy, Invited Talk in the Seminar Series Trends in Electronics, May 23, 2014.
[54] Michael Glaß, Michael Bader, Jürgen Teich and Stefan Wildermann. Assisting Run-time Optimization of Many-Core Systems by Design-time Characterization. HiPEAC Spring Computing Systems Week, Barcelona, Invited Talk, May 13, 2014.
[53] Jörg Henkel. The Dark Silicon Problem in Multi-Core Systems – Invasive Computing as a Solution. Keynote Talk, Thematic Session at HiPEAC Computer Systems Week, May 13,, 2014.
[52] Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann and Doris Schmitt-Landsiedel. Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture. In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), pages 14–15, May 2014.
[51] Manfred Kröhnert, Nikolaus Vahrenkamp, Johny Paul, Walter Stechele and Tamim Asfour. Resource Prediction for Humanoid Robots. In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), pages 22–28, May 2014.
[50] Vahid Lari, Alexandru Tanase, Frank Hannig and Jürgen Teich. Massively Parallel Processor Architectures for Resource-aware Computing. In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), pages 1–7, May 2014.
[49] Aurang Zaib, Prashanth Raju, Thomas Wild and Andreas Herkersdorf. A Layered Modeling and Simulation Approach to investigate Resource-aware Computing in MPSoCs. In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), pages 51–56, May 2014.
[48] Hannig, Frank and Teich, Jürgen, editors. Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014). , 2014.
[47] Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann and Wolfgang Schröder-Preikschat. OctoPOS: A Hardware-Assisted OS for Many-Cores. Poster presentation at the 9th European Conference on Computer Systems (EuroSys 2014) April 15, 2014.
[46] Jörg Henkel. Adaptive Embedded Computing with i-Core. Keynote Talk, 6th Workshop on Adaptive and Reconfigurable Embedded Systems, CPSWeek (APRES), April 14,, 2014.
[45] Carsten Tradowsky, Martin Schreiber, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz and Jürgen Becker. Towards Dynamic Cache and Bandwidth Invasion. In Reconfigurable Computing: Architectures, Tools, and Applications, 2014, Springer International Publishing, pages 97–107. [ DOI ]
[44] Deepak Gangadharan, Alexandru Tanase, Frank Hannig and Jürgen Teich. Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays. In DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES). ECSI, March 28, 2014. [ http ]
[43] Alcides Fonseca, Paulo Marques and Jonathan Aldrich. AEminium: A Permission Based Concurrent-by-Default Programming Language Approach. ACM Transactions on Programming Languages and Systems, 36(1):2:1–2:42, March 2014. [ DOI ]
[42] Muhammad Usman Karim Khan, Muhammad Shafique and Jörg Henkel. Software Architecture of High Efficiency Video Coding for Many-core Systems with Power-efficient Workload Balancing. In Design, Automation and Test in Europe (DATE), March 2014. [ DOI ]
[41] F. Sampaio, M. Shafique, B. Zatt, S. Bampi and J. Henkel. dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding. In Design, Automation and Test in Europe (DATE), March 2014. [ DOI ]
[40] Wolfgang Schröder-Preikschat. Embedded Computing Systems in the Multi-Core Era. Invited talk, University of Canterbury, Christchurch, New Zealand, March 7, 2014.
[39] Éricles Sousa, Vahid Lari, Johny Paul, Frank Hannig, Jürgen Teich and Walter Stechele. Resource-Aware Computer Vision Application on Heterogeneous Multi-Tile Architecture. Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March, 2014.
[38] Stefan Wildermann, Michael Glaß and Jürgen Teich. Multi-Objective Distributed Run-time Resource Management for Many-Cores. In Proceedings of Design, Automation and Test in Europe (DATE), pages 1-6, March 2014. [ DOI ]
[37] Wolfgang Schröder-Preikschat. Embedded Computing Systems in the Multi-Core Era. Invited talk, Victoria University of Wellington, New Zealand, February 28, 2014.
[36] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf and Jürgen Becker. The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. In Proceedings of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, February 25, 2014.
[35] Wolfgang Schröder-Preikschat. Embedded Computing Systems in the Multi-Core Era. Invited talk, Multicore World 2014, Auckland, New Zealand, February 25, 2014.
[34] Janmartin Jahn. Resource Allocation for Software Pipelines in Many-core Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2014.
[33] Michael Bader. On the Performance of Adaptive Mesh-Based Simulations on Modern HPC Architectures. Invited presentation at SIAM Conference on Parallel Processing in Scientific Computing - SIAM PP 2014, February, 2014. [ http ]
[32] Artjom Grudnitsky, Lars Bauer and Jörg Henkel. MORP: Makespan Optimization for Processors with an Embedded Reconfigurable Fabric. In Proceedings of the 22nd ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pages 127–136, February 2014. [ DOI ]
[31] Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann and Wolfgang Schröder-Preikschat. Resource-Aware Harris Corner Detection based on Adaptive Pruning. In Proceedings of the Conference on Architecture of Computing Systems (ARCS), pages 1–12. Springer, February 2014. [ DOI ]
[30] Sascha Roloff, Frank Hannig and Jürgen Teich. Towards Actor-oriented Programming on PGAS-based Multicore Architectures. In Workshop Proceedings of the 27th International Conference on Architecture of Computing Systems (ARCS). VDE Verlag, February 2014.
[29] C. Tradowsky, T. Gädeke, T. Bruckschlögl, W. Stork, K.-D. Müller-Glaser and J. Becker. SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor. In Parallel, Distributed and Network-Based Processing (PDP), 2014 22nd Euromicro International Conference on, pages 478-481, February 2014. [ DOI ]
[28] Michael Bader, Alexander Breuer, Wolfgang Hölzl and Sebastian Rettenberger. Vectorization of an Augmented Riemann Solver for the Shallow Water Equations. In Proceedings of the 2014 International Conference on High Performance Computing and Simulation (HPCS 2014), pages 193–201. IEEE, 2014.
[27] Martin Barke. Aging Aware Robustness Validation of Digital Integrated Circuits. Dissertation, Technische Universität München, Fakultät für Elektrotechnik und Informationstechnik, 2014.
[26] Matthias Braun, Sebastian Buchwald, Manuel Mohr and Andreas Zwinkau. Dynamic X10: Resource-Aware Programming for Higher Efficiency. Technical Report 8, Karlsruhe Institute of Technology, 2014. [ http ]
[25] Daniel Danner, Rainer Müller, Wolfgang Schröder-Preikschat, Wanja Hofer and Daniel Lohmann. Safer Sloth: Efficient, Hardware-Tailored Memory Protection. In Proceedings of the 20th IEEE International Symposium on Real-Time and Embedded Technology and Applications (RTAS '14), pages 37–47. IEEE Computer Society Press, 2014. [ http ]
[24] Felix Freiling, Mykola Protsenko and Yan Zhuang. An Empirical Evaluation of Software Obfuscation Techniques applied to Android APKs. In International Workshop on Data Protection in Mobile and Pervasive Computing, 2014.
[23] Stephanie Friederich, Jan Heisswolf, David May and Jürgen Becker. Hardware prototyping and software debugging of multi-core architectures. In Proceedings of the Synopsys Users Group Conference (SNUG), 2014.
[22] Johannes Götzfried and Tilo Müller. Mutual Authentication and Trust Bootstrapping towards Secure Disk Encryption. In Transactions on Information and System Security (TISSEC), 2014. [ DOI ] [ http ]
[21] Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann and Doris Schmitt-Landsiedel. Emulierung eines ASIC-Leistungsverbrauchs- und Temperaturmonitorsystems für FPGA-Prototyping eines ressourcengewahren Computersystems. In 16. Workshop Analogschaltungen, Wien, Österreich, 2014.
[20] E. Glocker, S. Boppu, Q. Chen, U. Schlichtmann, J. Teich and D. Schmitt-Landsiedel. Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs). Advances in Radio Science, 12:103–109, 2014. [ DOI ]
[19] Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase and Oliver Reiche. Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Transactions on Embedded Computing Systems (TECS), 13(4s):133:1–133:29, 2014. [ DOI ]
[18] Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf and Jürgen Becker. CAP: Communication Aware Programming. In 51th ACM/EDAC/IEEE Design Automation Conference (DAC), pages 105:1–105:6, 2014.
[17] Wanja Hofer. Sloth: The Virtue and Vice of Latency Hiding in Hardware-Centric Operating Systems. Dissertation, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2014. [ http ]
[16] Christopher Kugler and Tilo Müller. SCADS: Separated Control- and Data-Stacks (Best Student Paper Award). In 10th International Conference on Security and Privacy in Communication Networks, 2014. [ http ]
[15] Dominik Lorenz, Martin Barke and Ulf Schlichtmann. Monitoring of aging in integrated circuits by identifying possible critical paths. Journal of Microelectronics Reliability, 54:1075 - 1082, 2014. [ DOI ]
[14] David May and Walter Stechele. Improving the significance of probabilistic circuit fault emulations. In 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), pages 128–133, 2014.
[13] Rainer Müller, Daniel Danner, Wolfgang Schröder-Preikschat and Daniel Lohmann. MultiSloth: An Efficient Multi-Core RTOS using Hardware-Based Scheduling. In Proceedings of the 26th Euromicro Conference on Real-Time Systems (ECRTS '14), pages 289-198. IEEE Computer Society Press, 2014. [ DOI ]
[12] Roman Plyaskin. Fast and Accurate Performance Simulation of Out-of-order Processing Cores in Embedded Systems. Dissertation, Technische Universität München, Fakultät für Elektrotechnik und Informationstechnik, 2014.
[11] Nasim Pour Aryan, A. Listl, L. Heiss, C. Yilmaz, G. Georgakos and D. Schmitt-Landsiedel. From an analytic NBTI device model to reliability assessment of complex digital circuits. In International On-Line Testing Symposium (IOLTS), pages 19-24, 2014.
[10] Martin Schreiber. Cluster-Based Parallelization of Simulations on Dynamically Adaptive Grids and Dynamic Resource Management. Dissertation, Institut für Informatik, Technische Universität München, 2014. [ http ]
[9] Muhammad Shafique, Lars Bauer and Jörg Henkel. Adaptive Energy Management for Dynamically Reconfigurable Processors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 33(1):50–63, January 2014. [ DOI ]
[8] Muhammad Shafique and Jörg Henkel. Low Power Design of the Next-Generation High Efficiency Video Coding. In 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 274–281, January 2014. [ DOI ]
[7] Gregor Snelting, Dennis Giffhorn, Jürgen Graf, Christian Hammer, Martin Hecker, Martin Mohr and Daniel Wasserrab. Checking Probabilistic Noninterference Using JOANA. IT - Information Technology, 2014. invited article, currently under review [ http ]
[6] Tobias Weinzierl, Roland Wittmann, Kristof Unterweger, Michael Bader, Alexander Breuer and Sebastian Rettenberger. Hardware-aware block size tailoring on adaptive spacetree grids for shallow water waves. In HiStencils 2014 – 1st International Workshop on High-Performance Stencil Computations, 2014.
[5] Johny Paul, Walter Stechele, Manfred Kröhnert and Tamim Asfour. Resource-aware programming for robotic vision. arXiv preprint arXiv:1405.2908, First Workshop on Resource awareness and adaptivity in multi-core computing; co-located with IEEE European Test Symposium (ETS)2014.
[4] Martin Schreiber. Cluster-Based Parallelization of Simulations on Dynamically Adaptive Grids and Dynamic Resource Management. Dissertation, Technische Universität München, Fakultät für Informatik, 2014.
[3] D. Schiebener, A. Ude and T. Asfour. Physical Interaction for Segmentation of Unknown Textured and Non-textured Rigid Objects. In IEEE International Conference on Robotics and Automation (ICRA), 2014.
[2] Peter Kaiser, David Gonzalez-Aguirre, Fabian Schültje, J\'ulia Borr\`as, Nikolaus Vahrenkamp and Tamim Asfour. Extracting Whole-Body Affordances from Multimodal Exploration. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 1036–1043, 2014.
[1] M. Do, J. Schill, J. Ernesti and T. Asfour. Learn to Wipe: A Case Study of Structural Bootstrapping from Sensorimotor Experience. In IEEE International Conference on Robotics and Automation (ICRA), 2014.

2013

[80] Timo Stripf. Softwareframework für Prozessoren mit variablen Befehlssatzarchitekturen. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2013.
[79] Santiago Pagani and Jian-Jia Chen. Energy Efficient Task Partitioning based on the Single Frequency Approximation Scheme. In Proceedings of the 34th IEEE Real-Time Systems Symposium (RTSS), pages 308-318, December 2013. [ DOI ]
[78] Jürgen Teich. Invasive Computing – The Quest for Many-Core Efficiency and Predictability. Keynote Talk, Sixth Swedish Workshop on Multicore Computing, Halmstad, Sweden, November 25, 2013.
[77] Michael Bader. Exploiting locality properties of space-filling curves in scientific computing. Colloquium talk at TU Eindhoven, November, 2013.
[76] Muhammad Usman Karim Khan, Muhammad Shafique and Jörg Henkel. AMBER: Adaptive Energy Management for On-Chip Hybrid Video Memories. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 405–412, November 2013.
[75] Wolfgang Schröder-Preikschat. Embedded Computing Systems in the Multi-Core Era. Invited keynote, 3rd Brazilian Symposium on Computing Systems Engineering (SBESC 2013), Niterói, Brazil, November 5, 2013.
[74] Muhammad Shafique and Jörg Henkel. Agent-Based Distributed Power Management for Kilo-Core Processors. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 153–160, November 2013.
[73] Jürgen Teich. Invasive Computing - The Quest for Many-Core Efficiency and Predictability. Invited Talk, 5th tubs.CITY Symposium, Managing change and autonomy or critical applications, Braunschweig, Germany, October 30, 2013.
[72] Peter Figuli, Carsten Tradowsky, Nadine Gaertner and Jürgen Becker. ViSA: A Highly Efficient Slot Architecture Enabling Multi-Objective ASIP Cores. In International Symposium on System on Chip (SoC), pages 1–8, October 2013. [ DOI ]
[71] Manuel Mohr, Artjom Grudnitsky, Tobias Modschiedler, Lars Bauer, Sebastian Hack and Jörg Henkel. Hardware Acceleration for Programs in SSA Form. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2013. [ DOI ]
[70] Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann and Wolfgang Schröder-Preikschat. A Resource-Aware Nearest Neighbor Search Algorithm for K-Dimensional Trees. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages 80–87. IEEE Computer Society Press, October 2013.
[69] Martin Schreiber, Christoph Riesinger, Tobias Neckel and Hans-Joachim Bungartz. Invasive Compute Balancing for Applications with Hybrid Parallelization. In Proceedings of the International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). IEEE, October 2013.
[68] Martin Schreiber, Tobias Weinzierl and Hans-Joachim Bungartz. SFC-based Communication Metadata Encoding for Adaptive Mesh Refinement. In Proceedings of the International Conference on Parallel Computing (ParCo), October 2013.
[67] Éricles Sousa, Alexandru Tanase, Frank Hannig and Jürgen Teich. Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages 88–95. IEEE, October 2013.
[66] Éricles Sousa, Alexandru Tanase, Frank Hannig and Jürgen Teich. A Prototype of an Adaptive Computer Vision Algorithm on an MPSoC Architecture. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages 361–362. IEEE, October 2013.
[65] Tamim Asfour, Julian Schill, Heiner Peters, Cornelius Klas, Jens Bücker, Christian Sander, Stefan Schulz, Artem Kargov, Tino Werner and Volker Bartenbach. ARMAR-4: A 63 DOF Torque Controlled Humanoid Robot. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 390–396, October 2013.
[64] Jürgen Teich. The Invasive Computing Paradigm as a Solution for Highly Adaptive and Efficient Multi-core Systems. Talk, Special Session on Run-Time Adaption for Highly-Compley Multi-Core Systems, CODES+ISSS 2013, Montral, Canada, September 30, 2013.
[63] Wolfgang Schröder-Preikschat. Virtuelle Maschinen. Eingeladener Vortrag, INFORMATIK 2013, Workshop `Virtualisierung: gestern, heute und morgen', Koblenz, September 19, 2013.
[62] Elisabeth Glocker, Srinivas Boppu, Qingqing Chen, Ulf Schlichtmann, Jürgen Teich and Doris Schmitt-Landsiedel. Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs) on FPGA. In Kleinheubacher Tagung 2013, September 2013.
[61] Fazal Hameed, Lars Bauer and Jörg Henkel. Simultaneously Optimizing DRAM Cache Hit Latency and Miss Rate via Novel Set Mapping Policies. In International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES), September 2013. [ DOI ]
[60] Fazal Hameed, Lars Bauer and Jörg Henkel. Reducing Inter-Core Cache Contention with an Adaptive Bank Mapping Policy in DRAM Cache. In International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2013. [ DOI ]
[59] J. Heisswolf, S. Bischof, M. Rueckauer and Jürgen Becker. Efficient Memory Access in 2D Mesh NoC Architectures using High Bandwidth Routers. In Proceedings of the 26th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1-6, September 2013. [ DOI ]
[58] Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran and Jürgen Teich. Run-Time Adaptation for Highly-Complex Multi-Core Systems. In Proceedings of the IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2013. [ DOI ]
[57] Alexandru Tanase, Vahid Lari, Frank Hannig and Jürgen Teich. Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. In Proceedings of the International Conference on Parallel Computing (ParCo), pages 53–62, September 2013. [ DOI ]
[56] Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker and Andreas Herkersdorf. AUTO-GS: Self-optimization of NoC Traffic Through Hardware Managed Virtual Connections. In Proceedings of the 16th Euromicro Conference on Digital System Design (DSD), pages 761–768. IEEE, September 2013. [ DOI ]
[55] Gabor Drescher, Timo Hönig, Sebastian Maier, Benjamin Oechslein and Wolfgang Schröder-Preikschat. A Scalability-Aware Kernel Executive for Many-Core Operating Systems. In Proceedings of the International Workshop on Runtime and Operating Systems for the Many-core Era (ROME 2013), pages 1–10. Springer-Verlag, August 26, 2013.
[54] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf and Jürgen Becker. Virtual networks – distributed communication resource management. ACM Trans. Reconfigurable Technol. Syst., 6(2):8:1–8:14, August 2013. [ DOI ]
[53] Santiago Pagani and Jian-Jia Chen. Energy Efficiency Analysis for the Single Frequency Approximation (SFA) Scheme. In Proceedings of the 19th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pages 82-91, August 2013. \textbfBest Paper Award [ DOI ]
[52] Martin Schreiber, Tobias Weinzierl and Hans-Joachim Bungartz. Cluster Optimization and Parallelization of Simulations with Dynamically Adaptive Grids. In Euro-Par 2013, August 2013.
[51] Carsten Tradowsky, Tanja Harbaum, Shaver Deyerle and Jürgen Becker. LImbiC: An Adaptable Architecture Description Language Model for Developing an Application-Specific Image Processor. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 34–39, August 2013. [ DOI ]
[50] Srinivas Boppu, Frank Hannig and Jürgen Teich. Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators. In Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 10–17. IEEE, June 2013. [ DOI ]
[49] Janmartin Jahn, Santiago Pagani, Sebastian Kobbe, Jian-Jia Chen and Jörg Henkel. Optimizations for Configuring and Mapping Software Pipelines in ManyCore. In IEEE/ACM 50th Design Automation Conference (DAC), June 2013. [ DOI ]
[48] Vahid Lari, Srinivas Boppu, Frank Hannig, Jürgen Teich and Troy Scott. Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs. Designer Track Poster Presentation at the 50th Design Automation Conference (DAC), Austin, TX, USA, June, 2013.
[47] Sascha Roloff, Andreas Weichslgartner, Jan Heißwolf, Frank Hannig and Jürgen Teich. NoC Simulation in Heterogeneous Architectures for PGAS Programming Model. In Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems (M-SCOPES), pages 77–85. ACM, June 2013. [ DOI ]
[46] Amit Singh, Muhammad Shafique, Akash Kumar and Jörg Henkel. Mapping on Multi/Many Core Systems: Survey of Current and Emerging Trends. In IEEE/ACM 50th Design Automation Conference (DAC), June 2013. [ DOI ]
[45] Jürgen Teich, Alexandru Tanase and Frank Hannig. Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays. In Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 1–9. IEEE, June 2013. Best Paper Award [ DOI ]
[44] Srinivas Boppu, Vahid Lari, Frank Hannig and Jürgen Teich. Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures. In Proceedings of the Synopsys Users Group Conference (SNUG), May 14, 2013.
[43] Martin Barke, Veit B. Kleeberger, Christoph Werner, Doris Schmitt-Landsiedel and Ulf Schlichtmann. Analysis of Aging Mitigation Techniques for Digital Circuits Considering Recovery Effects. In edaWorkshop, May 2013.
[42] Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu and Jürgen Teich. System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures. In Proceedings of the ACM International Conference on Computing Frontiers (CF), pages 2:1–2:4. ACM, May 2013. [ DOI ]
[41] Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, T. Wild, A. Herkersdorf, Jürgen Teich and Jürgen Becker. Hardware Supported Adaptive Data Collection for Networks on Chip. In Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW), pages 153-162, May 2013. [ DOI ]
[40] Bruno Zatt, Muhammad Shafique, Sergio Bampi and Jörg Henkel. 3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures. In Springer Science+Business Media, LLC, May 2013.
[39] Jürgen Teich. Invasive Computing - The Quest for Many-Core Efficiency and Predictability. Invited Keynote, Doctoral Workshop GNARP 2013 (The 20th annual ASCI Computing Workshop), Soesterberg, The Netherlands, April 25, 2013.
[38] Jürgen Teich. More Cores = Less Predictability? Invited Talk, University of Amsterdam, The Netherlands, April 24, 2013.
[37] Jürgen Teich. More Cores = Less Predictability? Innovation Forum Smart Systems, Bavarian Information and Communication Technology Cluster (BICCNet), Munich, Germany, April 18, 2013.
[36] Éricles Sousa, Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich, Johny Paul, Walter Stechele, Manfred Kröhnert and Tamim Asfour. Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays. In Proceedings of the 25th Workshop on Parallel Systems and Algorithms (PARS), pages 80–89. Gesellschaft für Informatik e.V., April 2013.
[35] Janmartin Jahn and Jörg Henkel. Pipelets: Self-Organizing Software Pipelines for Many Core Architectures. In Proceedings of Design, Automation and Test in Europe Conference (DATE), March 2013. [ DOI ]
[34] Vahid Lari, Srinivas Boppu, Frank Hannig, Shravan Muddasani, Boris Kuzmin and Jürgen Teich. Resource-Aware Video Processing on Tightly-Coupled Processor Arrays. Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Grenoble, France, March, 2013. [ http ]
[33] Bing Li, Ning Chen, Yang Xu and Ulf Schlichtmann. On Timing Model Extraction and Hierachical Statistical Timing Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 32(3):367–380, March 2013.
[32] C. Pham, J. Heisswolf, S. Wenner, Z. Al-Ars, J.A. Becker and K.L.M. Bertels. Hybrid Interconnect Design for Heterogeneous Hardware Accelerators. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 843–846, March 2013. [ DOI ]
[31] Felipe Sampaio, Bruno Zatt, Muhammad Shafique, Luciano Agostini, Sergio Bampi and Jörg Henkel. Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 665-670, March 2013. [ DOI ]
[30] Muhammad Shafique, Benjamin Vogel and Jörg Henkel. Self-Adaptive Hybrid Dynamic Power Management for Many-Core Systems. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 51-56, March 2013. [ DOI ]
[29] Sefan Wildermann, Tobias Ziermann and Jürgen Teich. Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-core Systems. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 1498–1503, March 2013. [ DOI ]
[28] Frank Hannig. Resource-Aware Computing on Domain-Specific Accelerators. In Proceedings of the 10st Workshop on Optimizations for DSP and Embedded Systems (ODES), pages 35. ACM, February 24, 2013. Keynote [ DOI ]
[27] Jürgen Teich. Invasive Computing - The Quest for Many-Core Efficiency and Predictability. Invited Keynote Speech, 26th International Conference on Architecture of Computing Systems (ARCS), Prague, Czech Republic, February 20, 2013.
[26] Lars Braun. Methoden zur Erstellung eines laufzeitadaptiven und zweidimensional rekonfigurierbaren Systems. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2013.
[25] Jürgen Teich. Safe(r) Loop Computations on Multi-Cores. Invited Talk, 2nd Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms (DITAM 2013), Berlin, Germany, January 22, 2013.
[24] Matthias Braun, Sebastian Buchwald, Sebastian Hack, Roland Leißa, Christoph Mallon and Andreas Zwinkau. Simple and Efficient Construction of Static Single Assignment Form. In Compiler Construction, pages 102–122. Springer, 2013. [ DOI ]
[23] Hans-Joachim Bungartz, Christoph Riesinger, Martin Schreiber, Gregor Snelting and Andreas Zwinkau. Invasive Computing in HPC with X10. In X10 Workshop (X10'13), pages 12–19. ACM, 2013. [ DOI ]
[22] Patrick Flick, Peter Sanders and Jochen Speck. Malleable Sorting. In Parallel Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on, pages 418–426, 2013. [ DOI ]
[21] Elisabeth Glocker and Doris Schmitt-Landsiedel. Modeling of Temperature Scenarios in a Multicore Processor System. , 11:219–225, 2013. Advances in Radio Science (ARS), Volume 11 [ DOI ]
[20] Jan Heisswolf, Ralf König, M. Kupper and Jürgen Becker. Multiple Hard Latency and Throughput Guarantees for Packet Switching Networks on Chip. Computers & Electrical Engineering, 2013. [ DOI ]
[19] Jan Heisswolf, Maximilian Singh, Martin Kupper, Ralf Koenig and Juergen Becker. Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013.
[18] Reinhard Tartler. Mastering Variability Challenges in Linux and related Highly-Configurable System Software. Dissertation, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2013.
[17] Anil Kurmus, Reinhard Tartler, Daniela Dorneanu, Bernhard Heinloth, Valentin Rothberg, Andreas Ruprecht, Rüdiger Kapitza, Wolfgang Schröder-Preikschat and Daniel Lohmann. Attack Surface Metrics and Automated Compile-Time OS Kernel Tailoring. In Proceedings of the 20th Network and Distributed System Security Symposium (NDSS 2013), pages 1–8, 2013.
[16] Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid and Jürgen Teich. Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays. ACM Transactions on Design Automation of Electronic Systems (TODAES), 18(1):2:1–2:25, January 2013. [ DOI ]
[15] Yury Oleynik, Michael Gerndt and Andres Avila. A Data Model for Performance Dynamics Exploration. In 15th IEEE International Conference on High Performance Computing and Communications (HPCC-13), 2013.
[14] Luciano Ost, Rafael Garibotti, Gilles Sassatelli, Gabriel Marchesan Almeida, Remi Busseuil, Anastasiia Butko, Michel Robert and Jurgen Becker. Novel Techniques for Smart Adaptive Multiprocessor SoCs. IEEE Transactions on Computers, 99:1, 2013. PrePrints [ DOI ]
[13] Peter Sanders, Jochen Speck and Raoul Steffen. Work-efficient matrix inversion in polylogarithmic time. In Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures, pages 214–221. ACM, 2013. [ DOI ]
[12] Jürgen Teich, Wolfgang Schröder-Preikschat and Andreas Herkersdorf. Invasive Computing - Common Terms and Granularity of Invasion. CoRR, abs/1304.60672013.
[11] Josef Weidendorfer. Data Transfer Requirement Analysis with Bandwidth Curves. In Europar 2013 Workshop proceedings. 6th Workshop on Productivity and Performance, 2013.
[10] K. Welke, D. Schiebener, T. Asfour and R. Dillmann. Gaze selection during manipulation. In IEEE International Conference on Robotics and Automation (ICRA), 2013.
[9] Kai Welke, Nikolaus Vahrenkamp, Mirko Wächter, Manfred Kröhnert and Tamim Asfour. The ArmarX Framework - Supporting high level robot programming through state disclosure. In Informatik 2013 Workshop on robot control architectures, 2013.
[8] Martin Wirnshofer. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Series in Advanced Microelectronics, 2013.
[7] Tobias Ziermann. Self-organization and Optimization of Priority-based Communication Buses. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2013.
[6] Tobias Ziermann, Stefan Wildermann and Jürgen Teich. Self-organizing Core Allocation. In Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS). ACM German Chapter, Gesellschaft für Informatik e.V., 2013.
[5] Andreas Zwinkau, Sebastian Buchwald and Gregor Snelting. InvadeX10 Documentation v0.5. Technical Report 7, Karlsruhe Institute of Technology, 2013. [ http ]
[4] Martin Wirnshofer. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Dissertation, Technische Universität München, 2013.
[3] Marion Weinzierl. Hybrid Geometric-Algebraic Matrix-Free Multigrid on Spacetrees. Dissertation, Technische Universität München, Fakultät für Informatik, 2013.
[2] Job Noorman, Pieter Agten, Wilfried Daniels, Raoul Strackx, Anthony Van Herrewege, Christophe Huygens, Bart Preneel, Ingrid Verbauwhede and Frank Piessens. Sancus: Low-cost Trustworthy Extensible Networked Devices with a Zero-software Trusted Computing Base. In Proceedings of the 22nd USENIX Conference on Security, 2013.
[1] D. Schiebener, J. Morimoto, T. Asfour and A. Ude. Integrating visual perception and manipulation for autonomous learning of object representations. Adaptive Behavior, 21(5):328-345, 2013.

2012

[72] Wanja Hofer, Daniel Danner, Rainer Müller, Fabian Scheler, Wolfgang Schröder-Preikschat and Daniel Lohmann. Sloth on Time: Efficient Hardware-Based Scheduling for Time-Triggered RTOS. In Proceedings of the 33rd IEEE International Symposium on Real-Time Systems (RTSS '12), pages 237–247. IEEE Computer Society Press, December 2012. [ DOI ]
[71] Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner and Jürgen Becker. Determination of On-Chip Temperature Gradients on Reconfigurable Hardware. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pages 1–8, December 2012. [ DOI ]
[70] Martin Wirnshofer, Nasim Pour Aryan, Leonhard Heiss, Doris Schmitt-Landsiedel and Georg Georgakos. On-Line Supply Voltage Scaling based on In Situ Delay Monitoring to Adapt for PVTA Variations. Journal of Circuits, Systems and Computers, 21(08):December 2012. [ DOI ]
[69] Frank Hannig. Invasive Tightly-Coupled Processor Arrays. Talk, 1st International Workshop on Domain-Specific Multicore Computing (DSMC) at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 8, 2012.
[68] Frank Hannig. Why do we see more and more domain-specific accelerators in multi-processor systems? Guest Lecture at University of California, Riverside in CS 287 Colloquium in Computer Science, Riverside, CA, USA, November 9, 2012.
[67] Bing Li, Ning Chen and Ulf Schlichtmann. Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1670–1683, November 2012.
[66] David Schiebener, Julian Schill and Tamim Asfour. Discovery, Segmentation and Reactive Grasping of Unknown Objects. In 12th IEEE-RAS International Conference on Humanoid Robots (Humanoids), pages 71–77, November 2012.
[65] Jürgen Teich. Invasive Computing - or - How to Tame 1000+ Cores on a Chip? Invited Talk, IBM, Böblingen, Germany, October 26, 2012.
[64] Jürgen Teich. Invasive Computing - or - How to Tame 1000+ Cores on a Chip. Models and Assistive Tools for Programming Emerging Architectures, Invited Talk, HiPEAC CSW 2012, Ghent, Belgium, October 15, 2012.
[63] Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari and Jürgen Teich. A Prototype of an Invasive Tightly-Coupled Processor Array. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages 393–394. IEEE, October 2012.
[62] Wolfgang Schröder-Preikschat. Invasive Computing: A Systems-Programming Perspective. Invited talk, Université Pierre et Marie Curie (UPMC), Laboratoire d'Informatique de Paris (LIP6), Paris, September 28, 2012.
[61] Jürgen Teich. Invasive Computing - or - How to Tame 1000+ Cores on a Chip? Invited Talk, Intel, Braunschweig, Germany, September 20, 2012.
[60] N. Chen, B. Li and U. Schlichtmann. Iterative timing analysis based on nonlinear and interdependent flipflop modelling. Circuits, Devices Systems, IET, 6(5):330–337, September 2012. [ DOI ]
[59] Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild and Aurang Zaib. An Integrated Simulation Framework for Invasive Computing. In Proceedings of the Forum on Specification and Design Languages (FDL), pages 209–216. IEEE, September 2012.
[58] Michael Gerndt, Andreas Hollmann, Marcel Meyer, Martin Schreiber and Josef Weidendorfer. Invasive computing with iOMP. In Proceedings of the Forum on Specification and Design Languages (FDL), pages 225–231, September 2012.
[57] Jürgen Teich, Andreas Weichslgartner, Benjamin Oechslein and Wolfgang Schröder-Preikschat. Invasive Computing – Concepts and Overheads. In Proceedings of the Forum on Specification and Design Languages (FDL), pages 193–200, September 2012.
[56] Dominik Lorenz, Martin Barke and Ulf Schlichtmann. Efficiently analyzing the impact of aging effects on large integrated circuits. In Journal of Microelectronics Reliability, pages 1546–1552, August 2012. [ DOI ]
[55] Jürgen Teich. Invasive Computing - or - How to Tame 1000+ Cores on a Chip? Invited Talk, University of Auckland, New Zealand, August 9, 2012.
[54] Janmartin Jahn, Sebastian Kobbe, Santiago Pagani, Jian-Jia Chen and Jörg Henkel. Work in Progress: Malleable Software Pipelines for Efficient Many-core System Utilization. In Proceedings of the 6th Many-core Applications Research Community (MARC) Symposium, pages 30–33. ONERA, The French Aerospace Lab, July 19, 2012. [ http ]
[53] Christian Schuck. Design and Synthesis of Organic Computing Hardware Architectures. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2012.
[52] Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel and Jürgen Becker. Adaptive Processor Architecture. In International Conference on Embedded Computer Systems (SAMOS), pages 244–251, July 2012. Invited paper [ DOI ]
[51] Jan Heisswolf, Ralf König and Jürgen Becker. A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling. In Parallel and Distributed Processing with Applications (ISPA), 2012 IEEE 10th International Symposium on, pages 625–632, July 2012. [ DOI ]
[50] Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig and Jürgen Teich. Design of Low Power On-Chip Processor Arrays. In Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pages 165–168. IEEE Computer Society, July 2012. [ DOI ]
[49] Sascha Roloff, Frank Hannig and Jürgen Teich. Simulation of Resource-Aware Applications on Heterogeneous Architectures. In Proceedings of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), pages 127–130, July 2012.
[48] Alexandru Tanase, Frank Hannig and Jürgen Teich. Symbolic Loop Parallelization of Static Control Programs. In Proceedings of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), pages 33–36, July 2012.
[47] Jürgen Teich. Domain-specific and resource-aware computing on multi-core architectures. HiPEAC Summer School ACACES, Lecture, Lecture, Fiuggi, Italy, July 8, 2012.
[46] Stefan Wildermann. Systematic Design of Self-Adaptive Embedded Systems with Applications in Image Processing. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2012.
[45] Timo Hönig, Rüdiger Kapitza and Wolfgang Schröder-Preikschat. ProSEEP: A Proactive Approach to Energy-Aware Programming. June 2012. Poster.
[44] Matthias Kühnle. IP-based Reconfigurable System-on-Chip Design and Synthesis. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2012.
[43] Alexandru Tanase, Frank Hannig and Jürgen Teich. Towards Symbolic Loop Parallelization for Tightly-Coupled Processor Arrays. Work-In-Progress Presentation at the 49th Design Automation Conference (DAC), San Francisco, USA, June, 2012.
[42] Carsten Tradowsky, Florian Thoma, Michael Hübner and Jürgen Becker. LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture. In 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), pages 279–282, June 2012. Best Work-in-Progress (WiP) Paper Award [ DOI ]
[41] Jörg Henkel. i-Core: Adaptive Computing for Multi-core Architectures. Embedded System Design from MultiMedia to Cloud, Hong Kong, Invited Talk, May 18, 2012.
[40] Lars Bauer, Artjom Grudnitsky, Muhammad Shafique and Jörg Henkel. PATS: a Performance Aware Task Scheduler for Runtime Reconfigurable Processors. In 20th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 208–215, May 2012. [ DOI ]
[39] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf and Jürgen Becker. Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. In Proceedings of the 2012 IEEE 26th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW), pages 234–241, May 2012. [ DOI ]
[38] Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner and Wieland Eckert. Generating Device-specific GPU Code for Local Operators in Medical Imaging. In Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pages 569–581, May 2012. [ DOI ]
[37] Sascha Roloff, Frank Hannig and Jürgen Teich. Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation. In Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 52–61. ACM Press, May 2012. [ DOI ]
[36] Jürgen Teich. Hardware/Software Co-Design: The Past, Present, and Predicting the Future. Proceedings of the IEEE, 100(Centennial-Issue):1411–1430, May 2012. [ DOI ]
[35] Carsten Tradowsky, Florian Thoma, Michael Hübner and Jürgen Becker. On Dynamic Run-Time Processor Pipeline Reconfiguration. In IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), pages 419–424, May 2012. [ DOI ]
[34] Sani R. Nassif, Veit B. Kleeberger and Ulf Schlichtmann. Goldilocks failures: not too soft, not too hard. In IEEE International Reliability Physics Symposium (IRPS), April 2012.
[33] Martin Wirnshofer, Leonhard Heiss, A.N.Kakade, Nasim Pour Aryan, Georg Georgakos and Doris Schmitt-Landsiedel. Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. In IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pages 205–208, April 2012. [ DOI ]
[32] Jürgen Teich. Actor-Based Virtual Prototype Generation. Workshop: Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow, Invited Talk, date 2012, Dresden, Germany, March 16, 2012.
[31] Artjom Grudnitsky, Lars Bauer and Jörg Henkel. Partial online-synthesis for mixed-grained reconfigurable architectures. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 1555–1560, March 2012. [ DOI ]
[30] Christoph Knoth, Hela Jedda and Ulf Schlichtmann. Current Source Modeling for Power and Timing Analysis at Different Supply Voltages. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 923–928, March 2012. [ DOI ]
[29] Jürgen Teich. Introduction to Invasive Computing and Overhead Analysis for a Shared-Memory MPSoC. 3rd Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures, Munich, Germany, February 29, 2012.
[28] Reinhard Tartler, Julio Sincero, Christian Dietrich, Wolfgang Schröder-Preikschat and Daniel Lohmann. Revealing and Repairing Configuration Inconsistencies in Large-Scale System Software. International Journal on Software Tools for Technology Transfer (STTT), 14(5):531–551, February 2012. [ DOI ]
[27] Isañas A. Comprés Ureña, Michael Riepen, Michael Konow and Michael Gerndt. Invasive MPI on Intel's Single-Chip Cloud Computer. In Proceedings of the 25th International Conference on Architecture of Computing System (ARCS), pages 74–85. Springer, February 2012. [ DOI ]
[26] Josef Angermeier. Concepts and Algorithms to Increase the Efficiency and Reliability of Reconfigurable Computers. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2012.
[25] C. Böge, N. Vahrenkamp, T. Asfour and R. Dillmann. Visual Servoing for Single and Dual Arm Manipulation Tasks in Humanoid Robots. at - Automatisierungstechnik, 60(5):309–317, 2012.
[24] Michael Bader, Hans-Joachim Bungartz and Martin Schreiber. Invasive Computing on High Performance Shared Memory Systems. In Facing the Multicore-Challenge III, pages 1–12, 2012.
[23] Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf Koenig and David May. Hardware Prototyping of Novel Invasive Multicore Architectures. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 201–206, January 2012. [ DOI ]
[22] Matthias Braun, Sebastian Buchwald, Manuel Mohr and Andreas Zwinkau. An X10 Compiler for Invasive Architectures. Technical Report 9, Karlsruhe Institute of Technology, 2012. [ http ]
[21] Peter Figuli, Michael Hübner, Romuald Girardey, F. Bapp, Thomas Bruckschlögl, Florian Thoma, Jörg Henkel and Jürgen Becker. A heterogeneous SoC Architecture with embedded virtual FPGA Cores and runtime Core Fusion. In NASA/ESA 6th Conference on Adaptive Hardware and Systems (AHS), pages 96–103, 2012. [ DOI ]
[20] Dennis Giffhorn. Slicing of Concurrent Programs and its Application to Information Flow Control. Dissertation, Karlsruher Institut für Technologie, Fakultät für Informatik, 2012.
[19] Jens Gladigau. Combining Formal Model-Based System-Level Design with SystemC Transaction Level Modeling. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2012.
[18] Elisabeth Glocker and Doris Schmitt-Landsiedel. Modeling of Temperature Scenarios in a Multicore Processor System. In Kleinheubacher Tagung 2012, 2012.
[17] Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari and Sebastian Kobbe. Invasive Manycore Architectures. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 193–200, January 2012. [ DOI ]
[16] Julio Sincero. Variability Bugs in System Software. Dissertation, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2012.
[15] Andreas Hollmann and Michael Gerndt. Invasive Computing: An Application Assisted Resource Management Approach. In Multicore Software Engineering, Performance, and Tools, 2012, Springer Berlin Heidelberg, pages 82–85. [ DOI ]
[14] Daniel Lohmann, Olaf Spinczyk, Wanja Hofer and Wolfgang Schröder-Preikschat. The Aspect-Aware Design and Implementation of the CiAO Operating-System Family. In Transactions on AOSD IX, pages 168–215. Springer-Verlag, 2012. [ DOI ]
[13] Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour and Rüdiger Dillmann. Invasive Computing for Robotic Vision. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 207–212, January 2012. [ DOI ]
[12] Johny Paul, Andreas Laika, Christopher Claus, Walter Stechele, Adam El Sayed Auf and Erik Maehle. Real-time motion detection based on SW/HW-codesign for walking rescue robots. Journal of Real-Time Image Processing, :1–16, 2012. [ DOI ]
[11] Nasim Pour Aryan, Leonhard Heiss, Doris Schmitt-Landsiedel, Georg Georgakos and Martin Wirnshofer. Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling. Advances in Radio Science (ARS), 10:215–220, 2012.
[10] Sascha Roloff, Frank Hannig and Jürgen Teich. Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 187–192, January 2012. [ DOI ]
[9] Peter Sanders and Jochen Speck. Energy Efficient Frequency Scaling and Scheduling for Malleable Tasks. In Euro-Par 2012 Parallel Processing, 2012, Springer Berlin Heidelberg, pages 167–178. [ DOI ]
[8] Martin Schreiber, Hans-Joachim Bungartz and Michael Bader. Shared Memory Parallelization of Fully-Adaptive Simulations Using a Dynamic Tree-Split and -Join Approach. In Proceedings of HiPC 2012, pages 1–10. IEEE, 2012.
[7] Reinhard Tartler, Anil Kurmus, Andreas Ruprecht, Bernhard Heinloth, Valentin Rothberg, Daniela Dorneanu, Rüdiger Kapitza, Wolfgang Schröder-Preikschat and Daniel Lohmann. Automatic OS Kernel TCB Reduction by Leveraging Compile-Time Configurability. In Proceedings of the 8th Workshop on Hot Topics in System Dependability (HotDep '12), pages 3-3. USENIX Association, 2012.
[6] N. Vahrenkamp, T. Asfour and R. Dillmann. Simultaneous Grasp and Motion Planning. IEEE Robotics and Automation Magazine, 19(2):43–57, 2012.
[5] Shailesh More. Aging Degradation and Countermeasures in Deep-submicrometer Analog and Mixed Signal Integrated Circuits. Dissertation, Technische Universität München, 2012.
[4] Christoph Knoth. Accurate Waveform-based Timing Analysis with Systematic Current Source Models. Dissertation, Technische Universität München, 2012.
[3] Dominik Lorenz. Aging Analysis of Digital Integrated Circuits. Dissertation, Technische Universität München, 2012.
[2] Martin Roderus. Parallelization Strategies for Density Functional Software. Dissertation, Technische Universität München, Fakultät für Informatik, 2012.
[1] Vigh Csaba. Parallel Simulations of the Shallow Water Equations on Structured Dynamically Adaptive Triangular Grids. Dissertation, Technische Universität München, Fakultät für Informatik, 2012.

2011

[46] Alexander Klimm. Computing Architectures for Security Applications on Reconfigurable Hardware in Embedded Systems. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2011.
[45] Wanja Hofer, Daniel Lohmann and Wolfgang Schröder-Preikschat. Sleepy Sloth: Threads as Interrupts as Threads. In Proceedings of the 32nd IEEE International Symposium on Real-Time Systems (RTSS), pages 67–77. IEEE Computer Society, December 2011. [ DOI ]
[44] Dominik Lorenz, Martin Barke and Ulf Schlichtmann. Finding Possible Critical Paths for On-line Monitoring Of Aging in Integrated Circuits. Technical Report, Technische Universität München, 2011.
[43] Ravi Kumar Pujari, Thomas Wild, Andreas Herkersdorf, Benjamin Vogel and Jörg Henkel. Hardware Assisted Thread Assignment for RISC based MPSoCs in Invasive Computing. In Proceedings of the 13th International Symposium on Integrated Circuits (ISIC), pages 106-109, December 2011. [ DOI ]
[42] Martin Wirnshofer, Leonhard Heiss, Georg Georgakos and Doris Schmitt-Landsiedel. An Energy-Efficient Supply Voltage Scheme using In-Situ Pre-Error Detection for on-the-fly Adaptation to PVT Variations. In International Symposium on Integrated Circuits (ISIC), pages 94–97, December 2011. [ DOI ]
[41] Vahid Lari, Srinivas Boppu, Shravan Muddasani, Frank Hannig and Jürgen Teich. Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays. Talk, International Workshop on Adaptive Power Management with Machine Intelligence at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 10, 2011.
[40] Srinivas Boppu, Frank Hannig, Jürgen Teich and Roberto Perez-Andrade. Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pages 392–397. IEEE, November 2011. [ DOI ]
[39] M. Hübner, C. Tradowsky, D. Göhringer, L. Braun, F. Thoma, J. Henkel and J. Becker. Dynamic Processor Reconfiguration. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pages 123–128, November 2011. [ DOI ]
[38] Sebastian Kobbe, Lars Bauer, Jörg Henkel, Daniel Lohman and Wolfgang Schröder-Preikschat. DistRM: Distributed Resource Management for On-Chip Many-Core Systems. In Proceedings of the IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 119–128, October 2011. [ DOI ]
[37] Ning Chen, Bing Li and Ulf Schlichtmann. Timing Modeling of Flipflops Considering Aging Effects. In International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 63–72, September 2011.
[36] Christoph Knoth, Carsten Uphoff, Sebastian Kiesel and Ulf Schlichtmann. SWAT: Simulator for Waveform-Accurate Timing including Parameter Variations and Transistor Aging. In International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 193–203, September 2011.
[35] Vahid Lari, Andriy Narovlyanskyy, Frank Hannig and Jürgen Teich. Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays. In Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 87–94. IEEE Computer Society, September 2011. [ DOI ]
[34] Jürgen Teich. Programming Invasively Parallel – An Introduction. Pervasive Parallelism Laboratory (PPL) Seminar Talk, Stanford University, CA, USA, July 25, 2011.
[33] Jürgen Teich. Invasive Parallel Computing – An Introduction. Par Lab and AMP Lab Seminar Talk, UC Berkeley, CA, USA, July 22, 2011.
[32] Jörg Henkel, Lars Bauer, Michael Hübner and Artjom Grudnitsky. i-Core: A run-time adaptive processor for embedded multi-core systems. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), July 2011. Invited paper
[31] Veit B. Kleeberger and Ulf Schlichtmann. Reliability Analysis of Digital Circuits Considering Intrinsic Noise. In Asia Symposium on Quality Electronic Design (ASQED), July 2011.
[30] Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp and Jürgen Teich. Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor. In 3rd Many-core Applications Research Community (MARC) Symposium, pages 111–114. KIT Scientific Publishing, July 2011.
[29] Wolfgang Schröder-Preikschat. System Software in the Many-Core Era. Invited talk, Future Trends in SOC, Hasso-Plattner-Institut (HPI), Universität Potsdam, June 16, 2011.
[28] Lars Bauer, Muhammad Shafique and Jörg Henkel. Concepts, Architectures, and Run-time Systems for Efficient and Adaptive Reconfigurable Processors. In NASA/ESA 6th Conference on Adaptive Hardware and Systems (AHS), pages 80–87, June 2011. Invited paper; Received the MaXentric Technologies AHS Best Paper Award [ DOI ]
[27] Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich and Andreas Zwinkau. Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10. In Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 48–55. ACM Press, June 2011. [ DOI ]
[26] Johannes Zeppenfeld and Andreas Herkersdorf. Applying autonomic principles for workload management in multi-core systems on chip. In Proceedings of the 8th ACM International Conference on Autonomic Computing (ICAC), pages 3–10, June 2011. [ DOI ]
[25] Josef Angermeier, Eugen Sibirko, Rolf Wanka and Jürgen Teich. Bitonic Sorting on Dynamically Reconfigurable Architectures. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pages 309–312, May 2011.
[24] Michael Hübner, Peter Figuli, Romuald Girardey, Dimitrios Soudris, Kostas Siozios and Jürgen Becker. A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW), May 2011.
[23] Vahid Lari, Frank Hannig and Jürgen Teich. Distributed Resource Reservation in Massively Parallel Processor Arrays. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pages 318–321. IEEE Computer Society, May 2011. [ DOI ]
[22] Andreas Weichslgartner, Stefan Wildermann and Jürgen Teich. Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures. In Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages 201–208, May 2011. [ DOI ]
[21] Benjamin Oechslein, Jens Schedel, Jürgen Kleinöder, Lars Bauer, Jörg Henkel, Daniel Lohmann and Wolfgang Schröder-Preikschat. OctoPOS: A Parallel Operating System for Invasive Computing. In Proceedings of the International Workshop on Systems for Future Multi-Core Architectures (SFMA), pages 9–14, April 2011.
[20] Reinhard Tartler, Daniel Lohmann, Julio Cezar Rodrigues Sincero and Wolfgang Schröder-Preikschat. Feature Consistency in Compile-Time Configurable System Software. In Proceedings of the Sixth International ACM/EuroSys European Conference on Computer Systems (EuroSys), pages 47–60. ACM Press, April 2011. [ DOI ]
[19] J. Jahn, M.A. Al Faruque and Jörg Henkel. CARAT: Context-Aware Runtime Adaptive Task Migration for Multi Core Architectures. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 515–520, March 2011.
[18] Michael Bader, Hans-Joachim Bungartz, Michael Gerndt, Andreas Hollmann and Josef Weidendorfer. Invasive Programming as a Concept for HPC. In Proceedings of the 10th IASTED International Conference on Parallel and Distributed Computing and Networks 2011 (PDCN), February 2011. [ DOI ]
[17] Muhammad Shafique. Architectures for Adaptive Low-Power Embedded Multimedia Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2011.
[16] T. Asfour, M. Do, K. Welke, A. Bierbaum, P. Azad, N. Vahrenkamp, S. Gärtner, A. Ude and R. Dillmann. From sensorimotor primitives to manipulation and imitation strategies in humanoid robots. Springer Tracts in Advanced Robotics, 70(STAR):363–378, 2011.
[15] P. Azad, D. Münch, T. Asfour and R. Dillmann. 6-DoF Model-based Tracking of Arbitrarily Shaped 3D Objects. In IEEE International Conference on Robotics and Automation (ICRA), pages 5204–5209, 2011.
[14] Sebastian Buchwald, Andreas Zwinkau and Thomas Bersch. SSA-Based Register Allocation with PBQP. In Proceedings of the International Conference on Compiler Construction (CC), pages 42–61. Springer, 2011. [ DOI ]
[13] Hans-Joachim Bungartz, Bernhard Gatzhammer, Michael Lieb, Miriam Mehl and Tobias Neckel. Towards Multi-Phase Flow Simulations in the PDE Framework Peano. Computational Mechanics, 48(3):365–376, 2011. [ http ]
[12] Hritam Dutta. Synthesis and Exploration of Loop Accelerators for Systems-on-a-Chip. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2011.
[11] Michael Glaß. Dependability-Aware System-Level Design for Embedded Systems. Dissertation, University of Erlangen-Nuremberg, Germany, 2011.
[10] D. Hillerkuss, R. Schmogrow, T. Schellinger, M. Jordan, M. Winter, G. Huber, T. Vallaitis, R. Bonk, F. Kleinow, F. Frey, M. Roeger, S. Koenig, A. Ludwig, A. Marculescu, J. Li, M. Hoh, M. Dreschmann, J. Meyer, S. Ben Ezra, N. Narkiss, B. Nebendahl, F. Parmigiani, P. Petropoulos, B. Resan, A. Oehler, K. Weingarten, T. Ellermeyer, J. Lutz, M. Moeller, M. Huebner, J. Becker, C. Koos, W. Freude and J. Leuthold. 26 Tbit $s^-1$ line-rate super-channel transmission utilizing all-optical fast Fourier transform processing. nature photonics, (5):8, 2011. [ DOI ]
[9] Dmitrij Kissler. Power-Efficient Tightly-Coupled Processor Arrays for Digital Signal Processing. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2011.
[8] Dmitrij Kissler, Daniel Gran, Zoran A. Salcic, Frank Hannig and Jürgen Teich. Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays. IEEE Embedded Systems Letters, 3(2):58–61, 2011. [ DOI ]
[7] Veit B. Kleeberger, Martin Barke, Christoph Werner, Doris Schmitt-Landsiedel and Ulf Schlichtmann. A Compact Model for NBTI Degradation and Recovery under Use-Profile Variations and its Application to Aging Analysis of Digital Integrated Circuits. Microelectronics Reliability, 54(6–7):1083–1089, Jun 13, 2011. [ DOI ]
[6] Nasim Pour Aryan, Leonhard Heiss, Doris Schmitt-Landsiedel, Georg Georgakos and Martin Wirnshofer. Comparison of In-situ Delay Monitors for Use in Adaptive Voltage Scaling. In Kleinheubacher Tagung 2011, 2011.
[5] Peter Sanders and Jochen Speck. Efficient Parallel Scheduling of Malleable Tasks. In International Parallel and Distributed Processing Symposium (IPDPS), pages 1156–1166. IEEE Computer Society, 2011. [ DOI ]
[4] Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat and Gregor Snelting. Invasive Computing: An Overview. In Multiprocessor System-on-Chip – Hardware Design and Tool Integration, 2011, Springer, Berlin, Heidelberg, pages 241–268. [ DOI ]
[3] N. Vahrenkamp, P. Kaiser, T. Asfour and R. Dillmann. RDT+: A Parameter–free Algorithm for Exact Motion Planning. In IEEE International Conference on Robotics and Automation (ICRA), pages 715–722, 2011.
[2] Martin Wirnshofer, Leonard Heiss, Georg Georgakos and Doris Schmitt-Landsiedel. A Variation-Aware Adaptive Voltage Scaling Technique Based on In-Situ Delay Monitoring. In IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pages 261–266, 2011.
[1] Norbert Krüger, Christopher Geib, Justus Piater, Ronald Petrick, Mark Steedman, Florentin Wörgötter, Aleš Ude, Tamim Asfour, Dirk Kraft, Damir Omrŏen, Alejandro Agostini and Rüdiger f Dillmann. Object–Action Complexes: Grounded abstractions of sensory–motor processes. Robotics and Autonomous Systems, 59(10):740–757, 2011.

2010

[11] Frank Hannig. Retargetable Mapping of Loop Programs on Coarse-grained Reconfigurable Arrays. Talk, International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), Scottsdale, AZ, USA, October 26, 2010.
[10] Wolfgang Schröder-Preikschat. Systemsoftware im Zeitalter mehrkerniger Prozessoren. Vortrag October 15 2010. GI-Fachgruppe Betriebssysteme, IBM, Böblingen.
[9] A. Ude, A. Gams, T. Asfour and J. Morimoto. Task-Specific Generalization of Discrete and Periodic Dynamic Movement Primitives. IEEE Transactions on Robotics, 26(5):800–815, October 2010. [ DOI ]
[8] Tom Vander Aa, Praveen Raghavan, Scott Mahlke, Bjorn De Sutter, Aviral Shrivastava and Frank Hannig. Compilation Techniques for CGRAs: Exploring All Parallelization Approaches. In Proceedings of the International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), pages 185–186. ACM, October 2010. [ DOI ]
[7] Jürgen Teich. Invasive Computing – Basic Concepts and Foreseen Benefits. Artist Network of Excellence on Embedded System Design Summer School Europe 2010, Autrans, France, Invited Tutorial, September 7, 2010.
[6] Jürgen Teich. Invasive Computing – An Overview. The University of Sydney, Australia, Invited Talk, August 9, 2010.
[5] Jürgen Teich. Invasive Computing – A Novel Parallel Computing Paradigm. Workshop Multiprocessor System-On-Chip (MPSOC): Programmability, Run-Time Support and Hardware Platforms for High Performance Applications, 47th Design Automation Conference (DAC), Anaheim, USA, Invited Talk, June 13, 2010.
[4] Wolfgang Schröder-Preikschat. Systemsoftware im Zeitalter mehrkerniger Prozessoren. Vortrag April 23 2010. Innovation Forum Embedded Systems, BICC-NET, München.
[3] Wolfgang Schröder-Preikschat. Laufzeitsysteme mehrkerniger Prozessoren - Aspekte der Synchronisation in Betriebssystemen. Eingeladener Vortrag April 13 2010. Workshop zu Multicore Architecture and Programming Model Co-Optimization (MAPCO), TU München, Kloster Seeon.
[2] G. Frantz, J. Henkel, J. Rabaey, T. Schneider, M. Wolf and U. Batur. Ultra-Low Power Signal Processing. IEEE Signal Processing Magazine, 27(2):149–154, 2010. [ DOI ]
[1] Ralf Koenig, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Juergen Becker and Jörg Henkel. KAHRISMA: a novel hypermorphic reconfigurable-instruction-set multi-grained-array architecture. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 819–824. European Design and Automation Association, 2010.

2009

[13] Wolfgang Schröder-Preikschat. Systemsoftware im Zeitalter mehrkerniger Prozessoren. December 11 2009. Embedded Multi-Core Systems, Robert Bosch GmbH, Schwieberdingen.
[12] Amouri Abdulazim, Farhadur Arifin, Frank Hannig and Jürgen Teich. FPGA Implementation of an Invasive Computing Architecture. In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pages 135–142. IEEE, December 2009. [ DOI ]
[11] Christian Hammer and Gregor Snelting. Flow-Sensitive, Context-Sensitive, and Object-sensitive Information Flow Control Based on Program Dependence Graphs. International Journal of Information Security, 8(6):399–422, December 2009. [ DOI ]
[10] Wolfgang Schröder-Preikschat. Invasive Computing - Paralleles Betriebssystem einer SFB/TRR-Projektinitiative. Vortrag November 12 2009. GI-Fachgruppe Betriebssysteme, TU Dortmund, Universitätskolleg Bommerholz.
[9] Wolfgang Schröder-Preikschat. Systemsoftware im Zeitalter mehrkerniger Prozessoren. Eingeladener Vortrag November 3 2009. Vom Single-Core zum Multi-Core-Processing: Chancen und Herausforderungen für Eingebettete Systeme, Fraunhofer FIRST, Berlin.
[8] Farhadur Arifin, Richard Membarth, Amouri Abdulazim, Frank Hannig and Jürgen Teich. FSM-Controlled Architectures for Linear Invasion. In Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pages 59–64, October 2009. [ DOI ]
[7] Matthias Braun and Sebastian Hack. Register Spilling and Live-Range Splitting for SSA-Form Programs. In Proceedings of the International Conference on Compiler Construction (CC), pages 174–189. Springer, March 2009. [ DOI ]
[6] Wolfgang Schröder-Preikschat, Jörg Henkel, Lars Bauer and Daniel Lohmann. C1: Invasive Run-Time Support System ($i$RTSS). In , pages 471–528. In Teich et. al. ("Invasive Computing. "), pages 471–528.
[5] P. Azad, T. Asfour and R. Dillmann. Combining Harris Interest Points and the SIFT Descriptor for Fast Scale-Invariant Object Recognition. In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pages 4275–4280, 2009.
[4] P. Azad, T. Asfour and R. Dillmann. Accurate Shape-based 6-DoF Pose Estimation of Single-colored Objects. In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pages 2690–2695, 2009.
[3] Jürgen Teich and Sebastian Harl, editors. Invasive Computing. Funding Proposal. DFG Transregional Collaborative Research Centre 89, 2009.
[2] Tobias Weinzierl. A Framework for Parallel PDE Solvers on Multiscale Adaptive Cartesian Grids. Dissertation, Institut für Informatik, Technische Universität München, 2009. [ http ]
[1] Tobias Weinzierl. A Framework for Parallel PDE Solvers on Multiscale Adaptive Cartesian Grids. Dissertation, Technische Universität München, Fakultät für Informatik, 2009.

2008

[6] T. Asfour, K. Welke, P. Azad, A. Ude and R. Dillmann. The Karlsruhe Humanoid Head. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 447–453, December 2008.
[5] Michael Bader. Exploiting the Locality Properties of Peano Curves for Parallel Matrix Multiplication. August 2008.
[4] Mohammad Abdullah Al Faruque, Rudolf Krist and Jörg Henkel. ADAM: Run-time agent-based distributed application mapping for on-chip communication. In Proceedings of the 45th Design Automation Conference (DAC), pages 760–765, June 2008. [ DOI ]
[3] T. Asfour, P. Azad, N. Vahrenkamp, K. Regenstein, A. Bierbaum, K. Welke, J. Schröder and R. Dillmann. Toward Humanoid Manipulation in Human-Centred Environments. Robotics and Autonomous Systems, 56:54–65, 2008.
[2] Jürgen Teich. Invasive Algorithms and Architectures. it - Information Technology, 50(5):300–310, 2008.
[1] N. Vahrenkamp, S. Wieland, P. Azad, D. Gonzalez-Aguirre, T. Asfour and R. Dillmann. Visual Servoing for Humanoid Grasping and Manipulation Tasks. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 406–412, 2008.

2007

[1] Jürgen Becker, Michael Hübner, Gerhard Hettich, Rainer Constapel, Joachim Eisenmann and Jürgen Luka. Dynamic and Partial FPGA Exploitation. Proceedings of the IEEE, 95(2):438–452, February 2007. [ DOI ]