Projects


A1: Basics of Invasive Computing

Principal Investigators:

Prof. G. Snelting, Prof. J. Teich

Scientific Researchers:

Dr. J. Falk, Dr. F. Hannig, P. Mahmoody, B. Pourmohensi, T. Schwarzer, M. Wagner, Dr. S. Wildermann

Abstract

Project A1 investigates the basics of invasion, that is, the fundamental programming model for invasive and resource-aware computation as well as concepts, features and analysis of invasive programs and of run-time management strategies in invasive systems.

In the first funding phase, we investigated the fundamental programming model for invasive and resource-aware computation. Our research was divided into two major areas: The first area was devoted to the basic concepts, features, and analysis of invasive programs. The second area defined the language support for invasive programming concepts. The result of this phase was the invasive programming language InvadeX10 which is based on X10 and offers resource-aware programming and dynamic reservation of processor, memory, and communication bandwidth.

In the second funding phase, we exploited the effect of invasions to isolate applications from each other on future massively parallel processor systems to establish *-predictability. With this term, we understand the predictability of several non-functional properties of execution such as timeliness, security and fault tolerance on demand of a program or only for individual sections thereof. For this purpose, we introduced so-called requirements into the language. Such non-functional requirements are of ultimate importance for the applicability of multicore technology in the vast and growing market of embedded systems.

A strict isolation of resources, although allowing us to give even worst-case execution time guarantees for many applications on invasive computing architectures, may not always be desired because of over-provisioning resources or under-utilising them at times. One reason being the remaining variability of the above aspects also due to the uncertainty of input or the system itself, e.g. a power manager that may independently change the processor frequencies at any time. In the third funding phase, one of the main topics of investigation is run-time requirement enforcement (RRE) of non-functional properties of program execution. For this purpose, we will investigate (a) centralised vs. distributed run-time requirement enforcement, (b) strict vs. loose run-time requirement enforcement, (c) verification of run-time properties, and (d) formalising the X10 memory mode.

Synopsis

The static invasion of resources may provide desired bounded execution qualities (predictability), as was investigated in Phase II. Yet the price may still be high, as isolation alone may not reduce undesired jitters, e.g. in execution times, typically caused by uncertainty stemming from unknown or varying input and environmental execution conditions. Consequently, resources may be underutilised if claims are composed to reflect the worst case of input and environment. As a remedy, we want to investigate by which techniques requirements may be enforced at run time. This focal CRC topic is called Run-Time Requirement Enforcement (RRE).

Here, Project A1 will investigate novel centralised as well as distributed RRE techniques that will be based on sub-corridor partitioning. In the first, a central control instance shall be generated to enforce the desired non-functional qualities of execution based on statically analysed knowledge about the criticality and thus importance of certain design decisions such as computational requirements of an actor, etc. In the latter, requirement ranges shall be identified and statically partitioned into intervals called corridors. Moreover, in the case of hard requirements, techniques for strict enforcement shall be investigated. Here, sound formal proof techniques must be derived at compile time that an RRE technique will control a given program quality (e.g. by DVFS) to never leave a given requirement corridor.

An example of such a requirement to be verified is a hard execution deadline of an application graph as specified in ActorX10. Other important non-functional properties for which bounds shall be formally proven include memory requirements (tile-local and global memory), communication times, and load. In the case of soft requirements, temporal violations might be tolerable. Here, multi-objective control theory with the control laws derived from an analysis of the importances of tasks and their mapping on the quality under control may provide efficient enforcement solutions. Also, statistical analysis techniques might be candidates for loose requirement enforcement.

Approach

It might be difficult or even impossible for a programmer to specify by hand constraints on number and type of resources in order to achieve the desired quality of program execution, for example worst-case execution time. We therefore allow the programmer to specify requirements on execution qualities rather than constraints on resources. These requirements, such as a timing requirement of a maximal latency bound or a throughput requirement will be analysed at design time. We distinguish between soft and hard requirements. Hard requirements must never be violated for whatever reason. Whereas, soft requirements shall be satisfied most of the times, but their occasional violation may still be tolerated.

For predictable multicore program execution, we proposed a design flow which automatically determines claim constraints that will fulfil a set of given requirements, and then replaces the requirement pragmas in the source code by the respective set of claim constraints. The flow developed in cooperation with Project A4 implements a hybrid application mapping (HAM) approach for achieving run-time predictability by combining design-time analysis of application mappings with their run-time management as shown in the figure below.

Proposed hybrid application mapping.

Previous approaches to hybrid mapping focused on computation resources and either ignored communication details or made significantly simplifying assumptions like unlimited bandwidth or exclusive usage. But, actual manycore systems consist of constrained and shared computation and communication resources where the run-time decision of whether a feasible application binding on a set of preoccupied resources exists or not is an NP-complete problem. As a remedy, our hybrid application mapping approach considers constrained shared communication and computation resources. The developed methodology summarised in figure above consists of (a) a design space exploration (DSE) coupled with a formal performance analysis. This delivers several resource reservation configurations, so-called operating points, with verified satisfaction of the bounds as specified by requirements. The set of operating points is then transformed to (b) an efficient intermediate representation which can be expressed by constraints. This representation is passed to the run-time management by the invade-call. Assembling a claim adhering to these constraints is then the task of (c) run-time resource reservation (claim search and assignment).

In the area of language design and implementation, an actor-based language called ActorX10 has been defined on top of X10 in cooperation with Project A4 and Project C2. This actor-based description of applications with data-dependent tasks and requiring not only one or multiple cores, but different types of resources and also guaranteed communication bandwidth on NoC and to memory when executing, will also be a foundation to start our research on run-time requirement enforcement (RRE).

X10 provides the concept of a place as a shared memory domain within the language. Influenced from MPI, the major distributed HPC paradigm, X10 places were assumed static in number during the run time of a program. This assumption does not hold for programs invading and retreating from resources. Already in the first funding phase, we adapted the runtime to handle a changing number of places by adapting X10's runtime and standard library. In the second funding phase, we went further and changed language semantics: Each claim has its own view of places. This provides isolation between claims, which usually correspond with a notion of application. In X10, shared memory can be used for communication on the same tile. Between tiles, claims provide a method similar to infect. This provides language-level isolation between claims, which is the weakest level defined by Project C5, but the goal here is primarily to improve debugging and maintenance, not security.

A comprehensive summary of the major achievements of the first and second funding phase can be found by accessing Project A1 first phase and Project A1 second phase websites.

Publications

[1] Jörg Henkel, Jürgen Teich, Stefan Wildermann, and Hussam Amrouch. Dynamic Resource Management for Heterogeneous Many-Cores. In Proceedings of International Conference On Computer Aided Design 2018, November 2018.
[2] Jürgen Teich. Run-time application mapping in many-core architectures. Invited Talk National University of Singapore, August 24, 2018.
[3] Jürgen Teich. Mixed static/dynamic application mapping for NoC-based MPSoCs with guarantees on timing, reliability and security. Invited Talk Nanyang Technological University, Singapore, August 23, 2018.
[4] Jürgen Teich. Hybrid application mapping for NoC-based MPSoCs with guarantees on timing, reliability and security. Invited Talk University of New South Wales, Australia, July 31, 2018.
[5] Éricles R. Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, and Jürgen Teich. Invasive computing for predictability of multiple non-functional properties: A cyber-physical system case study. In Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, July 2018.
[6] Jürgen Teich. Methodologies for application mapping for noc-based mpsocs. Keynote, Adaptive Many-Core Architectures and Systems workshop, York, UK, June 14, 2018.
[7] Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jürgen Teich, and Michael Glaß. Architecture Decomposition in System Synthesis of Heterogeneous Many-Core Systems. In 55th ACM/EDAC/IEEE Design Automation Conference (DAC 2018), June 2018.
[8] Tobias Schwarzer, Andreas Weichslgartner, Michael Glaß, Stefan Wildermann, Peter Brand, and Jürgen Teich. Symmetry-eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(2):297–310, February 2018. doi: 10.1109/TCAD.2017.2695894. [ DOI ]
[9] Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, and Jürgen Teich. Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Springer, January 15, 2018. [ DOI ]
[10] Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, and Jürgen Teich. A design-time/run-time application mapping methodology for predictable execution time in mpsocs. ACM Transactions on Embedded Computing Systems (TECS), 2018. To appear.
[11] Tulika Mitra, Jürgen Teich, and Lothar Thiele. Guest Editors’ Introduction: Special Issue on Time-Critical Systems Design. IEEE Design and Test of Computers, 35:5–7, 2018. [ DOI ]
[12] Jürgen Teich. Application mapping methodologies for noc-based mpsocs. Invited Talk University of California, Irvine, USA, November 14, 2017.
[13] Jürgen Teich. Application mapping methodologies for noc-based mpsocs. Invited Talk University Lübeck, September 6, 2017.
[14] Andreas Weichslgartner. Application Mapping Methodologies for Invasive NoC-Based Architectures. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, January 24, 2017.
[15] Jürgen Teich. Run-time monitoring and enforcement of non-functional program properties of invasive programs: Terms and definitions. Technical Report 01-2017, Hardware/Software Co-Design, Friedrich-Alexander-Universität Erlangen-Nürnberg, Department of Computer Science, Erlangen, Germany, January 2017.
[16] Soonhoi Ha and Jürgen Teich, editors. The Handbook of Hardware/Software Codesign. Springer, 2017. [ DOI ]
[17] Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, and Jürgen Teich. Predictable run-time mapping reconfiguration for real-time applications on many-core systems. In Proceedings of the International Conference on Real-Time Networks and Systems (RTNS). IEEE, 2017. Outstanding paper award. [ DOI ]
[18] Jürgen Teich. Invasive computing – editorial. it – Information Technology, 58(6):263–265, November 24, 2016. [ DOI ]
[19] Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, and Andreas Zwinkau. Invasive computing for timing-predictable stream processing on MPSoCs. it – Information Technology, 58(6):267–280, September 30, 2016. [ DOI ]
[20] Gabor Drescher, Christoph Erhardt, Felix Freiling, Johannes Götzfried, Daniel Lohmann, Pieter Maene, Tilo Müller, Ingrid Verbauwhede, Andreas Weichslgartner, and Stefan Wildermann. Providing security on demand using invasive computing. it – Information Technology, 58(6):281–295, September 30, 2016. [ DOI ]
[21] Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner, and Stefan Wildermann. Language and compilation of parallel programs for *-predictable MPSoC execution using invasive computing. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pages 313–320, Lyon, France, September 2016. [ DOI ]
[22] Jürgen Teich. Predictability, fault tolerance, and security on demand using invasive computing. Invited Talk, University of Lübeck, Germany, July 29, 2016.
[23] Jürgen Teich. Invasive Computing - The DFG Transregional Research Center 89. DTC 2016, The Munich Workshop on Design Technology Coupling, Munich, Germany, June 30, 2016.
[24] Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, and Jürgen Teich. ActorX10: An actor library for X10. In Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10), pages 24–29. ACM, June 14, 2016. [ DOI ]
[25] Jürgen Teich. Predictable MPSoC stream processing using invasive computing. Seminar Talk, Electrical and Computer Engineering, The University of Texas at Austin, USA, June 6, 2016.
[26] Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix Freiling, Michael Glaß, and Jürgen Teich. Design-time/run-time mapping of security-critical applications in heterogeneous mpsocs. In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 153–162. ACM, May 23, 2016. [ DOI ]
[27] Andreas Weichslgartner and Jürgen Teich. Position paper: Towards redundant communication through hybrid application mapping. In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, April 4, 2016.
[28] Jürgen Teich. Adaptive restriction and isolation for predictable MPSoC stream procesing. Invited Talk, DATE 2016 Friday Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing, Dresden, Germany, March 18, 2016.
[29] Jürgen Teich. Symbolic loop parallelization for adaptive multi-core systems - recent advances and benefits. Keynote, IMPACT 2016, the 6th International Workshop on Polyhedral Compilation Techniques, 19 January, 2016, Prague, Czech Republic, January 19, 2016.
[30] Jürgen Teich. The role of restriction and isolation for increasing the predictability of MPSoC stream processing. Keynote, 8th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO 2016), Prague, Czech Republic, January 18, 2016.
[31] Stefan Wildermann. Time-predictable multi-core programming using invasive computing. Invited Talk at ESSEI TecDay: Multicore – The challenge in avionics, October 13, 2015.
[32] Sascha Roloff, Stefan Wildermann, Frank Hannig, and Jürgen Teich. Invasive computing for predictable stream processing: A simulation-based case study. In Proceedings of the 13th IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia). IEEE, October 2015. [ DOI ]
[33] Jürgen Teich. Adaptive isolation for predictable mpsoc stream processing. Keynote, SCOPES 2015, 18th International Workshop on Software and Compilers for Embedded Systems, Schloss Rheinfels, St. Goar, Germany, June 2, 2015.
[34] Jürgen Teich. Adaptive isolation for predictable mpsoc stream processing. In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2015), pages 1–2, June 2015. [ DOI ]
[35] Stefan Wildermann, Andreas Weichslgartner, and Jürgen Teich. Design methodology and run-time management for predictable many-core systems. In Proceedings of the 6th IEEE Workshop on Self-Organizing Real-Time Systems (SORT), pages 1–8, April 13, 2015.
[36] Stefan Wildermann. Wieviele prozessoren passen in eine hosentasche? Invited Talk at Öffentliche Vortragsreihe Faszination Technik, April 2015.
[37] Jürgen Teich. Invasive computing. Invited Talk, SE 2015, Software Engineering and Management, Special Session Software Engineering in der DFG, Dresden, Germany, March 19, 2015.
[38] Sebastian Buchwald, Manuel Mohr, and Andreas Zwinkau. Malleable invasive applications. In Proceedings of the 8th Working Conference on Programming Languages (ATPS), Lecture Notes in Computer Science (LNCS). Springer Berlin Heidelberg, March 2015.
[39] Jürgen Teich. Reconfigurable computing for mpsoc. Invited Lecture, Winter School Design and Applications of Multi Processor System on Chip, Tunis, Tunesia, November 26, 2014.
[40] Jürgen Teich. Invasive computing – concepts and benefits. Keynote, DASIP 2014, Conference on Design and Architectures for Signal and Image Processing, Madrid, Spain, October 8, 2014.
[41] Andreas Weichslgartner, Deepak Gangadharan, Stefan Wildermann, Michael Glaß, and Jürgen Teich. Daarm: Design-time application analysis and run-time mapping for predictable execution in many-core systems. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), pages 1–10, October 2014. [ DOI ]
[42] Jürgen Teich. System-level design automation of embedded systems. Invited Talk, Tagung Deutsche Forschungsgesellschaft für Automatisierung und Mikroelektronik e.V. (DFAM), September 25, 2014.
[43] Jürgen Teich. Foundations and benefits of invasive computing. Seminar, Mc Gill University, Montreal, July 29, 2014.
[44] Jürgen Teich. Introduction to invasive computing. Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), Paderborn, Germany, Tutorial Talk, May 29, 2014.
[45] Jürgen Teich. Foundations and benefits of invasive computing. University of Bologna, Italy, Invited Talk in the Seminar Series Trends in Electronics, May 23, 2014.
[46] Michael Glaß, Michael Bader, Jürgen Teich, and Stefan Wildermann. Assisting run-time optimization of many-core systems by design-time characterization. HiPEAC Spring Computing Systems Week, Barcelona, Invited Talk, May 13, 2014.
[47] Frank Hannig and Jürgen Teich, editors. Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014). May 2014. [ arXiv ]
[48] Deepak Gangadharan, Alexandru Tanase, Frank Hannig, and Jürgen Teich. Timing analysis of a heterogeneous architecture with massively parallel processor arrays. In DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES). ECSI, March 28, 2014. [ http ]
[49] Stefan Wildermann, Michael Glaß, and Jürgen Teich. Multi-objective distributed run-time resource management for many-cores. In Proceedings of Design, Automation and Test in Europe (DATE), pages 1–6, March 2014. [ DOI ]
[50] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, and Jürgen Becker. The invasive network on chip - a multi-objective many-core communication infrastructure. In Proceedings of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, February 25, 2014.
[51] Sascha Roloff, Frank Hannig, and Jürgen Teich. Towards actor-oriented programming on PGAS-based multicore architectures. In Workshop Proceedings of the 27th International Conference on Architecture of Computing Systems (ARCS). VDE Verlag, February 2014.
[52] Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, and Jürgen Becker. Cap: Communication aware programming. In 51th ACM/EDAC/IEEE Design Automation Conference (DAC), pages 105:1–105:6, 2014.
[53] Jürgen Teich. Invasive computing – the quest for many-core efficiency and predictability. Keynote Talk, Sixth Swedish Workshop on Multicore Computing, Halmstad, Sweden, November 25, 2013.
[54] Jürgen Teich. Invasive computing - the quest for many-core efficiency and predictability. Invited Talk, 5th tubs.CITY Symposium, Managing change and autonomy or critical applications, Braunschweig, Germany, October 30, 2013.
[55] Jürgen Teich. The invasive computing paradigm as a solution for highly adaptive and efficient multi-core systems. Talk, Special Session on Run-Time Adaption for Highly-Compley Multi-Core Systems, CODES+ISSS 2013, Montral, Canada, September 30, 2013.
[56] Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, and Jürgen Teich. Run-time adaptation for highly-complex multi-core systems. In Proceedings of the IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2013. [ DOI ]
[57] Jürgen Teich. Invasive computing - the quest for many-core efficiency and predictability. Invited Keynote, Doctoral Workshop GNARP 2013 (The 20th annual ASCI Computing Workshop), Soesterberg, The Netherlands, April 25, 2013.
[58] Jürgen Teich. More cores = less predictability? Invited Talk, University of Amsterdam, The Netherlands, April 24, 2013.
[59] Jürgen Teich. More cores = less predictability? Innovation Forum Smart Systems, Bavarian Information and Communication Technology Cluster (BICCNet), Munich, Germany, April 18, 2013.
[60] Sefan Wildermann, Tobias Ziermann, and Jürgen Teich. Game-theoretic analysis of decentralized core allocation schemes on many-core systems. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 1498–1503, March 2013. [ DOI ]
[61] Jürgen Teich. Invasive computing - the quest for many-core efficiency and predictability. Invited Keynote Speech, 26th International Conference on Architecture of Computing Systems (ARCS), Prague, Czech Republic, February 20, 2013.
[62] Jürgen Teich. Safe(r) loop computations on multi-cores. Invited Talk, 2nd Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms (DITAM 2013), Berlin, Germany, January 22, 2013.
[63] Hans-Joachim Bungartz, Christoph Riesinger, Martin Schreiber, Gregor Snelting, and Andreas Zwinkau. Invasive computing in HPC with X10. In X10 Workshop (X10'13), X10 '13, pages 12–19, New York, NY, USA, 2013. ACM. [ DOI ]
[64] Jürgen Teich, Wolfgang Schröder-Preikschat, and Andreas Herkersdorf. Invasive computing - common terms and granularity of invasion. CoRR, abs/1304.6067, 2013.
[65] Tobias Ziermann, Stefan Wildermann, and Jürgen Teich. Self-organizing core allocation. In Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS), number ISSN 0177-0454 in PARS Mitteilungen GI. ACM German Chapter, Gesellschaft für Informatik e.V., 2013.
[66] Andreas Zwinkau, Sebastian Buchwald, and Gregor Snelting. Invadex10 documentation v0.5. Technical Report 7, Karlsruhe Institute of Technology, 2013. [ .pdf ]
[67] Jürgen Teich. Invasive computing - or - how to tame 1000+ cores on a chip? Invited Talk, IBM, Böblingen, Germany, October 26, 2012.
[68] Jürgen Teich. Invasive computing - or - how to tame 1000+ cores on a chip. Models and Assistive Tools for Programming Emerging Architectures, Invited Talk, HiPEAC CSW 2012, Ghent, Belgium, October 15, 2012.
[69] Jürgen Teich. Invasive computing - or - how to tame 1000+ cores on a chip? Invited Talk, Intel, Braunschweig, Germany, September 20, 2012.
[70] Jürgen Teich, Andreas Weichslgartner, Benjamin Oechslein, and Wolfgang Schröder-Preikschat. Invasive computing – concepts and overheads. In Proceedings of the Forum on Specification and Design Languages (FDL), pages 193–200, September 2012.
[71] Jürgen Teich. Invasive computing - or - how to tame 1000+ cores on a chip? Invited Talk, University of Auckland, New Zealand, August 9, 2012.
[72] Jürgen Teich. Domain-specific and resource-aware computing on multi-core architectures. HiPEAC Summer School ACACES, Lecture, Lecture, Fiuggi, Italy, July 8, 2012.
[73] Jürgen Teich. Hardware/software co-design: The past, present, and predicting the future. Proceedings of the IEEE, 100(Centennial-Issue):1411–1430, May 2012. [ DOI ]
[74] Jürgen Teich. Actor-based virtual prototype generation. Workshop: Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow, Invited Talk, date 2012, Dresden, Germany, March 16, 2012.
[75] Jürgen Teich. Introduction to invasive computing and overhead analysis for a shared-memory mpsoc. 3rd Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures, Munich, Germany, February 29, 2012.
[76] Matthias Braun, Sebastian Buchwald, Manuel Mohr, and Andreas Zwinkau. An X10 compiler for invasive architectures. Technical Report 9, Karlsruhe Institute of Technology, 2012. [ http ]
[77] Jürgen Teich. Programming invasively parallel – an introduction. Pervasive Parallelism Laboratory (PPL) Seminar Talk, Stanford University, CA, USA, July 25, 2011.
[78] Jürgen Teich. Invasive parallel computing – an introduction. Par Lab and AMP Lab Seminar Talk, UC Berkeley, CA, USA, July 22, 2011.
[79] Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, and Jürgen Teich. Towards resource-aware programming on Intel's single-chip cloud computer processor. In 3rd Many-core Applications Research Community (MARC) Symposium, volume 7598 of KIT Scientific Reports, pages 111–114. KIT Scientific Publishing, July 2011.
[80] Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich, and Andreas Zwinkau. Resource-aware programming and simulation of MPSoC architectures through extension of X10. In Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 48–55. ACM Press, June 2011. [ DOI ]
[81] Andreas Weichslgartner, Stefan Wildermann, and Jürgen Teich. Dynamic decentralized mapping of tree-structured applications on NoC architectures. In Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages 201–208, May 2011. [ DOI ]
[82] Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat, and Gregor Snelting. Invasive computing: An overview. In Michael Hübner and Jürgen Becker, editors, Multiprocessor System-on-Chip – Hardware Design and Tool Integration, pages 241–268. Springer, Berlin, Heidelberg, 2011. [ DOI ]
[83] Jürgen Teich. Invasive computing – basic concepts and foreseen benefits. Artist Network of Excellence on Embedded System Design Summer School Europe 2010, Autrans, France, Invited Tutorial, September 7, 2010.
[84] Jürgen Teich. Invasive algorithms and architectures. it - Information Technology, 50(5):300–310, 2008.
[85] Andreas Zwinkau. Resource awareness for efficiency in high-level programming languages. Technical Report 12, Karlsruhe Institute of Technology. [ .pdf ]