Projects


B5: Invasive NoCs and Memory Hierarchies for Run-Time Adaptive MPSoCs

Principal Investigators:

Prof. J. Becker, Prof. A. Herkersdorf

Scientific Researchers:

N. Anantharajaiah, L. Masing, S. Rheindt, A. Srivatsa

Abstract

Project B5 investigates and designs the invasible Networks-on-a-Chip, in the following called iNoC.

In the first funding phase, a NoC architecture consisting of hardware modules and protocols was developed and implemented. This iNoC provides the possibility to invade communication resources. Through invasion of communication links, certain Quality-of-Service (QoS) guarantees can be given in terms of upper bounds for bandwidth and latency. Besides this elementary invasion capability, various decentralised and self-optimising mechanisms were investigated. Self-embedding, for instance, enables the decentralised hardware-assisted mapping of communication topologies. Rerouting helps to reduce congestion through remapping of connections and through monitoring of the traffic inside the network adapter links can be invaded autonomously (Auto-GS).

In the second funding phase, the focus of the scientific work shifted from a primarily functional design and implementation of invasion capabilities towards consideration of non-functional properties. This included topics like fault-tolerance, security, power management and dark silicon. The introduction of a lightweight second layer network allows coping with failing routers and can also be used to save energy by manually disabling regular tiles and routers on its path. Furthermore, the distributed memory architecture was improved by enabling applications to efficiently scale beyond tile borders through a novel region-based cache coherence (RBCC) scheme. RBCC provides scalable coherence for large MPSoCs by reducing administrative overheads compared to other, global coherence schemes.

In the third funding phase, Project B5 aims to dynamically adapt the interconnect infrastructure and the memory hierarchy of invasive architectures to optimize non-functional properties like performance or power efficiency. It will be investigated how to align the adaptations with invasive principles and QoS guarantees given by the network. The memory hierarchy will be improved by investigations into data locality optimisations including near-memory computing.

Synopsis

To fully exploit the benefits of invasive computing, the underlying network architecture should be flexible so that any application requirement can be accommodated. Project B5 will investigate techniques for run-time changes in the interconnect architecture by employing several network layers with varying topologies and also investigate the introduction of partial reconfiguration in the iNoC. A key element of research will be the question, how and on which subset of changes the iNoC. can hold and enforce its guarantees during and after any change in the architecture. To manage the adaptability and to optimize network and memory hierarchy special hardware units will be introduced, which employ various techniques to evaluate the current status and initiate run-time optimisations according to different metrics.
Since distributed-shared memory architectures exhibit NUMA properties, we further plan to tackle this data-to-task locality challenge by investigating data and task migration combined with near-memory computing for such hybrid distributed-shared memory system. We envision hardware-assisted migration of data and tasks at system run time, as well as the use of near-memory accelerator modules to improve data-to-task locality. The mutual influence of these techniques with region-based cache coherence will be investigated and a novel concept will be worked out for seamless interaction of these features.

Approach

We plan to investigate hierarchical topologies in both clustered and non-clustered approaches. It will help in increasing fault tolerance by providing redundancy due to the layered structure, on which single layers can also be disabled on demand to allow the enforcement of power ceilings. An example of how we envision clustered and non-clustered iNoC is shown.



To provide a fully flexible architecture, we propose to investigate several techniques that will allow us to change the network infrastructure at varying levels of granularity at run time. Among those techniques we envision the following: (a) Modifying the topology: One way is to change the network and select a topology from a set of predefined topologies. An alternative way is to modify an existing topology. This can be achieved by enabling or disabling links in the network. These unused link and router resources are then re-distributed amongst the layers of the network (b) Switching: A Combination of both packet and circuit switching where we envision a seamless architecture in which both techniques can be joined for the transmission of data. One option to achieve this would be based on additional local ports in each router, in which a packet could switch from the packet-switched network onto a circuit-switched connection that is established within the network. This way, link utilisation in circuit-switched connections can be increased, even while still guaranteeing throughput and latency constraints to the owner (i.e. the initiator) of the circuit. (c) Adaptive routing: In a static topology, adaptive routing will be the focus which, based on traffic load and other parameters, redirects the data to improve performance. In a topology which is changed at run time by, for example enabling and disabling the links, the routing algorithm in the routers is modified to support the changing topology.

To benefit from the newly gained flexibilities in the iNoC, self-management and self-organisation capabilities on either software or hardware level need to be employed. The requirement of any such self-x ability boils down to two parts: Firstly, an understanding of the current status of the system together with the relation between the provided configurations and the target metrics (e.g. requirements regarding non-functional properties of an application). Secondly, a management unit or entity, which can make decisions based on the gathered knowledge and subsequently trigger an adaptation. However, this is not sufficient for efficient execution on invasive architectures, since accommodating competing applications makes run-time knowledge necessary. We will achieve this by employing simple performance monitors, surveying (amongst others) buffer fill levels or virtual channel utilisation. Additionally, probes in the network can be utilised to determine resource availability ahead of time, using network internal communication to help in this process

Our near memory accelerators will implement specific functions in form of hardware that are directly executed on the data in the attached tile local memories and/or the global memory, thereby avoiding latency-costly memory transactions via the interconnect. The execution of NMA functions will occur interleaved with regular memory accesses from processor cores. Thereby, our target is to exploit the available memory bandwidth as much as possible and find a fair share between accesses from NMAs and from the processor cores. For integration into the manycore architecture the NMA modules take part in the coherency protocol of the processor cores including the bus-based invalidation on NMA write operations. For invalidating remote sharers due to the region-based coherency scheme as introduced in Project B5 second phase, an NMA module will therefore tightly interact with the coherency region manager (CRM), which keeps track of sharers within the coherency region.

In general, the goal of data migration is to reduce the number (and also the hop distance) of accesses to remote memories via the NoC within a coherency region. Data should dynamically be migrated to the TLM of the tile where the least latency and energy overhead is generated. To determine what data can be profitably moved and to which target tile, accesses to shared data are continuously monitored on page granularity. Dynamically established iNoC shortcut links or temporarily increased iNoC link bandwidths between source and target tiles will help to reduce migration time and thus make migration more profitable. In this context, an imminent data migration may also be a trigger for a reconfiguration of the iNoC. We will also study the coordination of data-migration with the iNoC self-organisation mechanisms. Dynamically moving data while they are being processed leads to the problem of guaranteeing the atomicity of the migration. We plan to use the diff NMA in tight collaboration with the iRTSS to solve this problem with the following two-step approach: First, the page is copied from its source tile to the target tile while read and write accesses are still allowed at its source tile. However, writes will be recorded by the NMA extension within a page diff until the copy is completed. In the second step, writes are prevented with the help of the iRTSS and the diff is transferred to and applied at the destination tile under the control of the two involved NMA modules. Then the associated page table entry of the migrated page will be updated and the corresponding TLB as well as cache entries will be invalidated by the iRTSS. After that, writes on the page are enabled again. We will study how the concrete interplay with the iRTSS has to occur to guarantee the atomicity of the transfer and also minimise migration costs. It is expected that transferring and applying the diff is much faster than copying the page, thus reducing the time where writes have to be blocked.

Achieved results

A comprehensive summary of the major achievements of the first and second funding phase can be found by accessing Project B5 first phase and Project B5 second phase websites.

Publications

[1] Jürgen Teich. Methodologies for application mapping for noc-based mpsocs. Keynote, Adaptive Many-Core Architectures and Systems workshop, York, UK, June 14, 2018.
[2] Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, and Jürgen Teich. Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Springer, January 15, 2018. [ DOI ]
[3] Tulika Mitra, Jürgen Teich, and Lothar Thiele. Guest Editors’ Introduction: Special Issue on Time-Critical Systems Design. IEEE Design and Test of Computers, 35:5–7, 2018. [ DOI ]
[4] Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild, and Andreas Herkersdorf. CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. In ARCS 2018 - 31st International Conference on Architecture of Computing Systems, Braunschweig, Germany, 2018.
[5] Leonard Masing, Akshay Srivatsa, Fabian KreB, Nidhi Anantharajaiah, Andreas Herkersdorf, and Jurgen Becker. In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures. In 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, sep 2018. [ DOI ]
[6] A. Srivatsa, S. Rheindt, T. Wild, and A. Herkersdorf. Region based cache coherence for tiled mpsocs. In 2017 30th IEEE International System-on-Chip Conference (SOCC), September 2017.
[7] Stephanie Friederich. Automated Hardware Prototyping for 3D Networks on Chips. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), May 23, 2017.
[8] Lukas Meder. Timing Synchronization and Fast-Control for FPGA-based large-scale Readout and Processing Systems. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), April 1, 2017.
[9] Andreas Weichslgartner. Application Mapping Methodologies for Invasive NoC-Based Architectures. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, January 24, 2017.
[10] Soonhoi Ha and Jürgen Teich, editors. The Handbook of Hardware/Software Codesign. Springer, 2017. [ DOI ]
[11] Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, and Andreas Herkersdorf. Efficient task spawning for shared memory and message passing in many-core architectures. Journal of Systems Architecture (JSA), 2017. [ DOI ]
[12] Jürgen Teich. Invasive computing – editorial. it – Information Technology, 58(6):263–265, November 24, 2016. [ DOI ]
[13] Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, and Dibyendu Ghoshal. A novel image impulse noise removal algorithm optimized for hardware accelerators. Journal of Signal Processing Systems, 89(2):225–242, November 1, 2016. [ DOI ]
[14] Vahid Lari, Andreas Weichslgartner, Alex Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jürgen Becker, Jan Heißwolf, and Stephanie Friederich. Providing fault tolerance through invasive computing. it – Information Technology, 58(6):309–328, October 19, 2016. [ DOI ]
[15] Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, and Andreas Zwinkau. Invasive computing for timing-predictable stream processing on MPSoCs. it – Information Technology, 58(6):267–280, September 30, 2016. [ DOI ]
[16] Gabor Drescher, Christoph Erhardt, Felix Freiling, Johannes Götzfried, Daniel Lohmann, Pieter Maene, Tilo Müller, Ingrid Verbauwhede, Andreas Weichslgartner, and Stefan Wildermann. Providing security on demand using invasive computing. it – Information Technology, 58(6):281–295, September 30, 2016. [ DOI ]
[17] Stephanie Friederich, Marco Neber, and Jürgen Becker. Power management controller for online power saving in network-on-chips. In International Symposium on Embedded Multicore/Manycore SoCs (MCSoC), volume 10, September 2016.
[18] Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner, and Stefan Wildermann. Language and compilation of parallel programs for *-predictable MPSoC execution using invasive computing. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pages 313–320, Lyon, France, September 2016. [ DOI ]
[19] Jürgen Teich. Predictability, fault tolerance, and security on demand using invasive computing. Invited Talk, University of Lübeck, Germany, July 29, 2016.
[20] Jürgen Teich. Invasive Computing - The DFG Transregional Research Center 89. DTC 2016, The Munich Workshop on Design Technology Coupling, Munich, Germany, June 30, 2016.
[21] Jürgen Teich. Predictable MPSoC stream processing using invasive computing. Seminar Talk, Electrical and Computer Engineering, The University of Texas at Austin, USA, June 6, 2016.
[22] Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix Freiling, Michael Glaß, and Jürgen Teich. Design-time/run-time mapping of security-critical applications in heterogeneous mpsocs. In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 153–162. ACM, May 23, 2016. [ DOI ]
[23] Jan Heisswolf, Stephanie Friederich, Leonard Masing, Aandreas Weichslgartner, Aurang M. Zaib, Carsten Stein, Marco Duden, Jürgen Teich, Thomas Wild, Andreas Herkersdorf, and Jürgen Becker. A novel noc-architecture for fault tolerance and power saving. In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, April 4, 2016.
[24] Andreas Weichslgartner and Jürgen Teich. Position paper: Towards redundant communication through hybrid application mapping. In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, April 4, 2016.
[25] Jürgen Teich. Adaptive restriction and isolation for predictable MPSoC stream procesing. Invited Talk, DATE 2016 Friday Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing, Dresden, Germany, March 18, 2016.
[26] Jürgen Teich. Symbolic loop parallelization for adaptive multi-core systems - recent advances and benefits. Keynote, IMPACT 2016, the 6th International Workshop on Polyhedral Compilation Techniques, 19 January, 2016, Prague, Czech Republic, January 19, 2016.
[27] Jürgen Teich. The role of restriction and isolation for increasing the predictability of MPSoC stream processing. Keynote, 8th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO 2016), Prague, Czech Republic, January 18, 2016.
[28] Stephanie Friederich, Niclas Lehmann, and Jürgen Becker. Adaptive bandwidth router for 3d network-on-chips. In Applied Reconfigurable Computing, pages 352–360, 2016. [ DOI ]
[29] Michael Dreschmann, Jan Heisswolf, Michael Geiger, Manuel Haußecker, and Jürgen Becker. A framework for multi-FPGA interconnection using multi gigabit transceivers. In Proceedings of the 28th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 5:1–5:6. ACM, August 2015. [ DOI ]
[30] Moritz Schmid. Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, July 24, 2015.
[31] Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klöpfer, Thomas Wild, Andreas Herkersdorf, Jürgen Teich, and Jürgen Becker. Fault-tolerant communication in invasive networks on chip. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pages 1–8. IEEE, June 2015.
[32] Jürgen Teich. Adaptive isolation for predictable mpsoc stream processing. Keynote, SCOPES 2015, 18th International Workshop on Software and Compilers for Embedded Systems, Schloss Rheinfels, St. Goar, Germany, June 2, 2015.
[33] Stefan Wildermann, Andreas Weichslgartner, and Jürgen Teich. Design methodology and run-time management for predictable many-core systems. In Proceedings of the 6th IEEE Workshop on Self-Organizing Real-Time Systems (SORT), pages 1–8, April 13, 2015.
[34] Preethi Parayil, Aurang Zaib, Thomas Wild, Stefan Wallentowitz, and Andreas Herkersdorf. Sharer status-based caching in tiled multiprocessor systems-on-chip. In HPC 2015 – 23rd High Performance Computing Symposia, pages 67–74. SCS, The Society for Modeling & Simulation, April 2015.
[35] Jürgen Teich. Invasive computing. Invited Talk, SE 2015, Software Engineering and Management, Special Session Software Engineering in der DFG, Dresden, Germany, March 19, 2015.
[36] Andreas Weichslgartner, Jan Heisswolf, Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jürgen Becker, and Jürgen Teich. Position paper: Towards hardware-assisted decentralized mapping of applications for heterogeneous noc architectures. In Proceedings of the second International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, March 2015.
[37] Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, and Andreas Herkersdorf. Network interface with task spawning support for noc-based dsm architectures. In 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS), volume 9017 of Lecture Notes in Computer Science (LNCS), pages 186–198. Springer, 2015. [ DOI ]
[38] Christoph Roth. Parallele und kooperative Simulation für eingebettete Multiprozessorsysteme. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), December 2014. [ http ]
[39] Jürgen Teich. Reconfigurable computing for mpsoc. Invited Lecture, Winter School Design and Applications of Multi Processor System on Chip, Tunis, Tunesia, November 26, 2014.
[40] Jan Heisswolf. A Scalable and Adaptive Network on Chip for Many-Core Architectures. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), November 11, 2014. [ http ]
[41] Jürgen Teich. Invasive computing – concepts and benefits. Keynote, DASIP 2014, Conference on Design and Architectures for Signal and Image Processing, Madrid, Spain, October 8, 2014.
[42] Andreas Weichslgartner, Deepak Gangadharan, Stefan Wildermann, Michael Glaß, and Jürgen Teich. Daarm: Design-time application analysis and run-time mapping for predictable execution in many-core systems. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), pages 1–10, October 2014. [ DOI ]
[43] Stephanie Friederich, Jan Heisswolf, and Jürgen Becker. Hardware/software debugging of large scale many-core architectures. In Proceedings of the 27th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1–7. IEEE, September 2014. [ DOI ]
[44] Jürgen Teich. Foundations and benefits of invasive computing. Seminar, Mc Gill University, Montreal, July 29, 2014.
[45] Jürgen Teich. Introduction to invasive computing. Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), Paderborn, Germany, Tutorial Talk, May 29, 2014.
[46] Jürgen Teich. Foundations and benefits of invasive computing. University of Bologna, Italy, Invited Talk in the Seminar Series Trends in Electronics, May 23, 2014.
[47] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, and Jürgen Becker. The invasive network on chip - a multi-objective many-core communication infrastructure. In Proceedings of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, February 25, 2014.
[48] Stephanie Friederich, Jan Heisswolf, David May, and Jürgen Becker. Hardware prototyping and software debugging of multi-core architectures. In Proceedings of the Synopsys Users Group Conference (SNUG), 2014.
[49] Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, and Jürgen Becker. Cap: Communication aware programming. In 51th ACM/EDAC/IEEE Design Automation Conference (DAC), pages 105:1–105:6, 2014.
[50] J. Heisswolf, S. Bischof, M. Rueckauer, and Jürgen Becker. Efficient memory access in 2d mesh noc architectures using high bandwidth routers. In Proceedings of the 26th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1–6, September 2013. [ DOI ]
[51] Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, and Andreas Herkersdorf. Auto-gs: Self-optimization of noc traffic through hardware managed virtual connections. In Proceedings of the 16th Euromicro Conference on Digital System Design (DSD), pages 761–768. IEEE, September 2013. [ DOI ]
[52] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, and Jürgen Becker. Virtual networks – distributed communication resource management. ACM Trans. Reconfigurable Technol. Syst., 6(2):8:1–8:14, August 2013. [ DOI ]
[53] Sascha Roloff, Andreas Weichslgartner, Jan Heißwolf, Frank Hannig, and Jürgen Teich. NoC simulation in heterogeneous architectures for PGAS programming model. In Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems (M-SCOPES), pages 77–85. ACM, June 2013. [ DOI ]
[54] Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, T. Wild, A. Herkersdorf, Jürgen Teich, and Jürgen Becker. Hardware supported adaptive data collection for networks on chip. In Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW), pages 153–162, May 2013. [ DOI ]
[55] C. Pham, J. Heisswolf, S. Wenner, Z. Al-Ars, J.A. Becker, and K.L.M. Bertels. Hybrid interconnect design for heterogeneous hardware accelerators. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 843–846, March 2013. [ DOI ]
[56] Jürgen Teich. Safe(r) loop computations on multi-cores. Invited Talk, 2nd Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms (DITAM 2013), Berlin, Germany, January 22, 2013.
[57] Jan Heisswolf, Ralf König, M. Kupper, and Jürgen Becker. Multiple hard latency and throughput guarantees for packet switching networks on chip. Computers & Electrical Engineering, 2013. [ DOI ]
[58] Jan Heisswolf, Maximilian Singh, Martin Kupper, Ralf Koenig, and Juergen Becker. Rerouting: Scalable noc self-optimization by distributed hardware-based connection reallocation. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013.
[59] Christian Schuck. Design and Synthesis of Organic Computing Hardware Architectures. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), July 10, 2012.
[60] Jan Heisswolf, Ralf König, and Jürgen Becker. A scalable noc router design providing qos support using weighted round robin scheduling. In Parallel and Distributed Processing with Applications (ISPA), 2012 IEEE 10th International Symposium on, pages 625–632, July 2012. [ DOI ]
[61] Matthias Kühnle. IP-based Reconfigurable System-on-Chip Design and Synthesis. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), June 6, 2012.
[62] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, and Jürgen Becker. Hardware-assisted decentralized resource management for networks on chip with qos. In Proceedings of the 2012 IEEE 26th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW), pages 234–241, Shanghai, China, May 2012. [ DOI ]
[63] Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf Koenig, and David May. Hardware prototyping of novel invasive multicore architectures. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 201–206, January 2012. [ DOI ]
[64] Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, and Sebastian Kobbe. Invasive manycore architectures. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 193–200, January 2012. [ DOI ]
[65] Alexander Klimm. Computing Architectures for Security Applications on Reconfigurable Hardware in Embedded Systems. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), December 22, 2011.
[66] Andreas Weichslgartner, Stefan Wildermann, and Jürgen Teich. Dynamic decentralized mapping of tree-structured applications on NoC architectures. In Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages 201–208, May 2011. [ DOI ]
[67] Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat, and Gregor Snelting. Invasive computing: An overview. In Michael Hübner and Jürgen Becker, editors, Multiprocessor System-on-Chip – Hardware Design and Tool Integration, pages 241–268. Springer, Berlin, Heidelberg, 2011. [ DOI ]
[68] Jürgen Teich. Invasive algorithms and architectures. it - Information Technology, 50(5):300–310, 2008.