InvasIC News & Activities

Events 2023

Best Paper Award at MEMOCODE'23,
September 21-22, 2023, Hamburg

The paper "Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers" (Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann and Jürgen Teich) has won the Best Paper Award at ESWEEK 2023's 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE) in Hamburg, Germany.
In their work, the authors propose a novel design space exploration methodology that uses a combination of evolutionary algorithms and reinforcement learning to efficiently find verifiable feedback-based controllers for non-functional requirements such as latency or energy. The approach is shown to significantly reduce exploration time and to outperform existing methods in generating controllers with higher probabilities of meeting verification goals in three case studies. The paper originated as part of TRR 89 Invasive Computing.

Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann and Jürgen Teich have received the Best Paper Award at MEMOCODE'23 (Photo: FAU/Andreas Bininda)

Embedded Talk "Non-volatile memory technologies and applications",
September 13, 2023, DAU

On Wednesday, September 13, 2023, the 16th Embedded Talk was held for the first time again in presence at FAU in Erlangen. The topic was "Non-volatile memory technologies and applications". Many participants took the opportunity to exchange information about current research and developments in this field.
After a welcome by ESI speaker Prof. Dr.-Ing. Jürgen Teich, Dr.-Ing. Stefan Slesazeck (Senior Scientist at NaMLab gGmbH, Dresden) started with his keynote on "Ferroelectric memories for neuromorphic computing". Afterwards, Prof. Dr.-Ing. Christian Hochberger (Chair for Computer Systems, TU Darmstadt) addressed memristor-based FPGAs and their opportunities and risks in his keynote. Inspired by the exciting keynotes and refreshed by a coffee break, panel discussion moderated by Prof. Dr.-Ing. Jürgen Teich introduced the interactive part of the event. In addition to the two keynote speakers, Prof. Dr.-Ing. Dietmar Fey (FAU) also participated in the discussion on the podium. The lively discussions then continued during the poster session, where 8 exhibitors from the two DFG priority programs SPP 2262 ("Memristive Devices for Intelligent Technical Systems") and SPP 2377 ("Disruptive Main Memory Technologies") reported on their projects.
For some of the participants, it was their first exchange with researchers from the other DFG SPP. Thus, the event provided important networking opportunities especially for PhD students from FAU ESI.

Prof. Teich welcoming the guests (Photo: FAU/Andreas Bininda)

Keynote speaker Dr. Slezazeck, NaMLab gGmbH (Photo: FAU/Andreas Bininda)

Prof. Teich moderating the Panel Discussion with Prof. Hochberger, Prof. Fey and Dr. Slesazeck (Photo: FAU/Andreas Bininda)

Student delegation from Osaka University, Japan, visiting FAU,
September 11-12, 2023

On September 11 and 12, a group of selected delegates studying in various engineering programs at Osaka University, FAU's partner university, visited Erlangen. The visit was coordinated by Prof. Kiyoshi Fujita, Director of the Center for International Relations of the Graduate School of Engineering, and Ms. Ikuko Nojiri.
The group was hosted by the Chair of Computer Science 12 (Hardware-Software-Co-Design) of Prof. Jürgen Teich. Thanks also to Daniel Seidel, a student of computer science at FAU, for his help in also coordinating the visit. Mr. Seidel was able himself to enjoy a stay at Osaka University during the past semester as part of the Maple exchange program.

Student delegation from Osaka University visiting the Chair of Computer Science 12

Hardware/Software Co-Design Team designs Supercomputer-on-a-Chip

A team of the Hardware/Software Co-Design Chair designed a chip that integrates 64 custom processor cores.

A board for testing the developed chip. Picture: FAU/Andreas Bininda

The chip, called ALPACA, unleashes an enormous computing power of up to 384 billion arithmetic operations per second while drawing less than 3 watts.
ALPACA’s application domains are manifold. The chip is suitable for the fast processing of digital signals (audio, video) as well as large amounts of data, such as those present in machine learning and scientific computing. Thanks to its low power demands, applications in the fields of medical technology, IoT systems, and automotive benefit in particular.
ALPACA was developed within the Collaborative Research Centre/Transregio 89 “Invasive Computing,” funded by the German Research Foundation (DFG). The area of the chip is just 10 mm2, manufactured in 22 nm semiconductor technology. However, a chip is only as powerful as its corresponding compilation and programming tools. Therefore, in a unique hardware/software co-design, a powerful compiler for parallelization and automatic mapping of loop programs has been developed parallel to the chip design.

The developer team. Picture: FAU/Andreas Bininda

EDAA Outstanding Dissertation Award, DATE 2023,
April 18, 2023, Antwerp

Dr.-Ing. Martin Rapp (KIT)

Martin Rapp, has received the EDAA Outstanding Dissertation Award 2023 at DATE 2023 for his outstanding dissertation entitled "Machine Learning for Resource-Constrained Computing Systems".

DATE 2023 Party Award Session,
April 18, 2023, Antwerp

Prof. Dr.-Ing. Jürgen Teich (FAU)

Professor Jürgen Teich was awarded the DATE Fellow Award at the Award Session of the Design Automation & Test in Europe (DATE) conference 2023. He has received this award for distinguishing himself in the DATE organization team over many years, especially for his leadership role as General Chair of DATE 2019 in Florence.

Prof. Dr.-Ing. Jürgen Teich reveiving his DATE Fellow Award, Copyright DATE, Cruz Garcia

Opening Ceremony Session DATE 2023,
April 17, 2023, Antwerp

Prof. Dr.-Ing. Jürgen Teich (FAU)

Professor Teich presented several prestigious EDA (Electronic Design Automation) awards as Awards Chair at the Design Automation & Test in Europe (DATE) conference 2023.

Prof. Dr.-Ing. Jürgen Teich at the Opening Ceremony Session, Copyright DATE, Cruz Garcia

PhD Forum DATE 2023,
April 17, 2023, Antwerp

Marcel Brand (FAU)

Marcel Brand presented his research results with a poster at the PhD Forum at the Design Automation & Test in Europe (DATE) conference 2023 in Antwerp. The conference was held in presence for the first time since 2019. Many attendees were interested to learn about his work and innovative processor architecture concepts for processor arrays.

Marcel Brand presenting his poster at the DATE 2023 PHD Forum

Events 2022

Best Paper Award at SBESC'22,
November 21-24,2022, Fortaleza, Brasilien

Benedikt Jung, Christian Eichler, Jonas Röckl, Ralph Schlenk, Prof. Dr.-Ing. Timo Hönig, Prof. Dr.-Ing. Tilo Müller

Timo Hönig (RUB) and his research group received a Best Paper Award for the work "Trusted Monitor: TEE-Based System Monitoring" at the XII Brazilian Symposium on Computing Systems Engineering (SBESC'22).

Dissertation Award for Dr.-Ing. Behnaz Pourmohseni,
November 18,2022, Erlangen

Dr.-Ing. Behnaz Pourmohseni (FAU)

At the occasion of the Day of the Faculty of Engineering 2022, Mrs. Behnaz Pourmohseni is awarded the ATE Alumni Dissertation Award for her thesis "System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems".

Dr.-Ing. Behnaz Pourmohseni receiving her Dissertation Award

InvasIC Colloquium, October 6-7, 2022, Erlangen

More than twelve years of collaborative research on Invasive Computing found a celebratory ending at the Fraunhofer IIS, where it all began.
On this occasion, researchers, reviewers, experts and alumni met for the InvasIC Colloquium.

Agenda of the InvasIC Colloquium

Professor Teich opened the InvasIC Colloquium and welcomed the guests. He then gave an overview talk of the last 12.5 years of collaborative research in the field of Invasive Computing.

Prof. Teich opened the InvasIC Colloquium

After that, the guests had the opportunity to network and to visit the exhibition of the subprojects and Global Demonstrators. Each subproject presented its research with a scientific poster. The highlight of the exhibiton were the four Global Demonstrators, which made the research visible for everyone.

Global Demonstrators

Come together at the InvasIC Colloquium

The day finally came to a festive ending at the evening event with an italian dinner, musical performances and presentations from selected alumni.

Evening event with dinner and entertainment

On the second day of the InvasIC Colloquium, Prof. Dr. Vijaykrishnan Narayanan from Penn State University gave a Keynote Talk about "Moving Compute to Data: Resurgence of Processing in Memory Architectures". After that, four experts of the industry board took a stand on the question of „How relevant are many-core architectures, and in particular their compliance to non-functional requirements, in your own professional area?”

Keynote Talk of Prof. Dr. Vijaykrishnan Narayanan

Invasive Computing at the Hannover Messe

May 30 - June 2, 2022

Christian Heidorn and Torsten Klie at Hannover Messe 2022

Our Transregional Collaborative Research Center Invasive Computing showed together with the FAU Research Center Embedded Systems Initiative (FAU ESI) a demonstrator for hand sign recognition via Deep Learning on tightly-coupled processor arrays (TCPAs) as part of the BayernInnovativ joint booth at the Hannover Messe 2022.
The interest in the "Future Hub" in Hall 2 was unbroken and the traffic at the booth was comparable to previous years.

Events 2021

58th Design Automation Conference (DAC'21), San Francisco, USA, December 5-9, 2021:

Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT)

Prof. Dr.-Ing. Jörg Henkel was the Conference Program Chair of the 58th Design Automation Conference (DAC'21).
more information

Scopus data bank: Rank 30 and 39 in Hardware & Architecture, November 9, 2021:

Prof. Dr.-Ing. Jörg Henkel (KIT) & Prof. Dr.-Ing. Jürgen Teich (FAU)

According to new evaluation of the Scopus data bank done by the Stanford University, Prof. Dr.-Ing. Jörg Henkel ranks on place 30 and Prof. Dr.-Ing. Jürgen Teich ranks on place 39 of the most cited scientists in the science field of hardware and architecture. Congratulations!
more information

ICCAD 2021 hosting 6th Workshop on Approximate Computing, November 4, 2021

Prof. Dr.-Ing. Jürgen Teich (FAU)

Together with Alexandra Kourfali, University of Stuttgart, Alberto Bosio, Ecole Centrale de Lyon, and Alessandro Savino, Politecnico di Torino, Jürgen Teich was chairing the 6th Workshop on Approximate. The virtual event was co-located this year with ICCAD 2021.

Dagstuhl Seminar 21441 (former 20291)
"Adaptive Resource management for HPC Systems", Schloss Dagstuhl, November 1-5, 2021:

Prof. Dr. Michael Gerndt (TUM), Masaaki Kondo (University of Tokyo, Japan), Barton P. Miller (University of Wisconsin, USA) and Tapasya Patki (LLNL, USA)

Participants of the Dagstuhl Seminar 21441, November 1-5, 2021.

This Dagstuhl Seminar investigated a holistic, layered approach for adaptive resource management. It started with the resource management layer being responsible for scheduling applications on the machine and dynamically allocating resources to the running applications. At the programming level, applications need to be programmed in a resource-aware style such that they can adapt to resource changes and can make most efficient usage of the resources. On top of the programming interfaces, programming tools have to be available that allow the application developers to analyze and tune the applications for the varying amount of available resources. At the application level, applications have to be redesigned to enable significant gains in efficiency and throughput, e.g., adaptive mesh refinement, approximate computing, and power-aware algorithms are a few aspects to mention here. The outcomes of this seminar were a list of challenges and a roadmap that identified the next steps for implementing adaptive resource management of HPC systems including languages, message passing libraries, resource managers, tools, and runtimes.
more information

HiPEAC Computing Week, Lyon, October 25, 2021:

Opening Keynote: Enforcement of Non-functional Program Requirements on MPSoCs

Prof. Dr.-Ing. Jürgen Teich (FAU)

Hosted by the University of Lyon, this Computing Systems Week brings the HiPEAC community together with the *systems-on-chip and embedded systems/connected objects research group at CNRS*, see here for details

Prof. Dr.-Ing. Jürgen Teich (FAU) giving the opening keynote speech at the HiPEAC Computing Week.

Many embedded applications require non-functional requirements such as safety, reliability, and execution time to be guaranteed during the execution of respective programs on modern Multi-Processor System-on-Chip (MPSoC) platforms. Unfortunately, current compilers and operating systems are not aware of such requirements and thus no able to satisfy, or even counter-productive in satisfying these, e.g., by sharing resources unnecessarily between application programs and thus creating execution interference.

In this talk, we first introduce the concept and principles of Invasive Computing that allows a programmer to claim a set of resources exclusively, e.g., CPU cores, for each application. Importantly, this not only creates an on-demand isolation of elsewise interfering programs, but as a result allows to then apply static analysis and optimization techniques to optimize the deployment of applications on a given MPSoC. Unfortunately, jitter and variability of non-functional program execution qualities such as, e.g., latency or throughput may still remain to a certain degree due do either exogeneous noise influences such as data-dependent input workload, but also induced currently by MPSoC-internal system management software, e.g., dynamic power management. As a remedy, we presented novel techniques named Run-time Requirement Enforcement (RRE) to support the satisfaction of given non-functional execution requirements for individual applications in tight bounds at run-time. These are based on Enforcement Automata. These sense the incoming workload variation at run-time while adjusting core and power management in reaction. It was shown that these can be generated and even formally verified statically prior to their deployment for run-time control of a given set of requirements. For image and other types of streaming applications, we provided intuitive examples that by controlling DVFS settings of invaded CPU cores either pro-actively or re-actively, not only tight execution times, but also power corridors may be strictly enforced, or alternatively the number of violations or return times to satisfaction of requirements minimized.

G'SCHEID SCHLAU!, October 23, 2021:

Franziska Schirrmacher (FAU)

Franziska Schirrmacher took part in a discussion on AI together with the Minister of Science Bernd Sibler and Professor Markus Kaiser from TH Nürnberg. The event was part of the series "Siblers DenkRäume" where Bernd Sibler engages in conversations with citizens about current socially relevant topics such as artificial intelligence (AI). The discussion revolved around the topic "KI... und ich? Von der Bilderkennung bis zu Social Media. KI in unseren Medien". It was on the agenda of "G'SCHEID SCHLAU !" and took place at the Deutsches Museum Nürnberg. As a doctoral researcher, Franziska is currently developing AI methods for side channel detection in the TRR 89.
To find out more, you can watch the video of the discussion here.

Institut des nanotechnologies de Lyon (INL), September 14, 2021:

Invited Talk: Enforcement of Non-functional Program Requirements on MPSoCs

Prof. Dr.-Ing. Jürgen Teich (FAU)

Many embedded applications require non-functional requirements such as safety, reliability, and execution time to be guaranteed during the execution of respective programs on modern Multi-Processor System-on-Chip (MPSoC) platforms. Unfortunately, current compilers and operating systems are not aware of such requirements and thus no able to satisfy, or even counter-productive in satisfying these, e.g., by sharing resources unnecessarily between application programs and thus creating execution interference.

In this talk, we first introduced the concept and principles of Invasive Computing that allows a programmer to claim a set of resources exclusively, e.g., CPU cores, for each application. Importantly, this not only creates an on-demand isolation of elsewise interfering programs, but as a result allows to then apply static analysis and optimization techniques to optimize the deployment of applications on a given MPSoC. Unfortunately, jitter and variability of non-functional program execution qualities such as, e.g., latency or throughput may still remain to a certain degree due do either exogeneous noise influences such as data-dependent input workload, but also induced currently by MPSoC-internal system management software, e.g., dynamic power management. As a remedy, we presented novel techniques named Run-time Requirement Enforcement (RRE) to support the satisfaction of given non-functional execution requirements for individual applications in tight bounds at run-time. These are based on Enforcement Automata. These sense the incoming workload variation at run-time while adjusting core and power management in reaction. It was shown that these can be generated and even formally verified statically prior to their deployment for run-time control of a given set of requirements. For image and other types of streaming applications, we provided intuitive examples that by controlling DVFS settings of invaded CPU cores either pro-actively or re-actively, not only tight execution times, but also power corridors may be strictly enforced, or alternatively the number of violations or return times to satisfaction of requirements minimized.

NUERNBERG DIGITAL 2021: Digital Gender Gap

Dr. Sandra Mattauch and Franziska Schirrmacher (FAU)

Once a year, the Nuremberg Digital Festival connects people in the Nuremberg metropolitan region for ten days on the central topics of digitization in business, science, education and culture. The festival sees itself as an open participatory format for the digital community: regional organizations take part as organizers to exchange knowledge and discuss the opportunities and risks of the digital society. In the realm of the Nuremberg Digital Festival Sandra Mattauch and Franziska Schirrmacher from our Transregio, were interviewed regarding the topic “The Gender Gap” in informatics. See the full article on page 22.

NUERNBERG DIGITAL 2021: Digital Gender Gap

Nomination for KI-Newcomer 2021

Franziska Schirrmacher (FAU)

Franziska was nominated for KI-Newcomer 2021. As a doctoral researcher she is currently developing AI methods for side channel detection in the TRR 89. To find out more, read Franziskas interview with FAU aktuell here.

Member of the German Society of Humboldtians, Virtual Event, February 18, 2021:

Prof. Dr.-Ing. Jürgen Teich (FAU)

The German Society of Humboldtians (www.dgh-ev.org) welcomes Jürgen Teich as a new member for his merits as a host of Humboldtians, reviewer for the Humboldt Foundation (AvH) and his numerous contacts to and stays at foreign universities.

DATE Friday Workshop SLOHA 2021, Virtual Workshop, February 5, 2021:

Dr.-Ing. Frank Hannig (Hardware/Software Co-Design, FAU)

On February 5, 2021, the first "DATE Friday Workshop System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021)" took place co-located with the Conference on Design, Automation and Test in Europe (DATE). The SLOHA Workshop, initiated and co-organized by Frank Hannig, addressed machine learning topics on heterogeneous computing architectures (e.g., dedicated accelerators, GPUs, FPGAs) and autonomous vehicles. The workshop program consisted of keynote talks (Luca Benini, ETH Zurich on "In-Sensor ML - Heterogeneous Computing in a mW" and Michaela Blott, Xilinx Research on "Specialization in Hardware Architectures for Deep Learning") and peer-reviewed submissions. Furthermore, results of the BMBF-funded project "KISS: AI Laboratory for System-level Design of ML-based Signal Processing Applications" (https://www.iis.fraunhofer.de/kiss)/ were presented. The substantial number of 76 registered participants reflected the very topics and attractiveness of the workshop program.
More information is available on the SLOHA 2021 website: https://www12.cs.fau.de/ws/sloha2021/.

Organizing Committee of the DATE Friday Workshop SLOHA, February 5, 2021.

Siemens Master Prize, Virtual Event, February 5, 2021:

Armin Schuster (FAU)

Armin Schuster was honored on February 5, 2021 as part of the virtual graduation ceremony of the technical faculty. For his master's thesis "Design Space Exploration of Approximate CNN-Inference with Variable Precision", supervised by Professor Teich, from Siemens / Corporate Technology, he received the Siemens Master Prize in the Information and Communication Technology course.

more information

Invasic Computing at HiPEAC Computer Systems Week 2021, Virtual Conference, January 20, 2021:

Invited Talk: A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems

Prof. Dr.-Ing. Jürgen Teich (FAU)

Prof. Teich give an invited talk within the Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021) at HiPEAC Computer Systems Week 2021.

more information

Events 2020

MLCAD 2020: 2nd ACM/IEEE Workshop on Machine Learning for CAD:

Prof. Dr.-Ing. Ulf Schlichtmann (Chair of Electronic Design Automation, TUM)

November 16-20, 2020: Prof. Dr.-Ing. Ulf Schlichtmann (TUM) served as General Chair of 2nd ACM/IEEE Workshop on Machine Learning for CAD (MLCAD 2020).
Advances in machine learning (ML) over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However, design processes present challenges that require parallel advances in ML and CAD as compared to traditional ML applications such as image classification. As such, the purpose of the workshop is to discuss, define and provide a roadmap for the special needs for ML for CAD where CAD is broadly defined as design-time techniques as well as run-time techniques.

more information

IEEE CEDA Presentation Library:

Jan Spieck, Dr.-Ing. Stefan Wildermann and Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

November 11, 2020, The IEEE Council on Electronic Design Automation (CEDA) is a centralized resource for viewing videos and presentations from conferences, webinars, and lecturers. The video presentation "Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs" Prof. Teich held during the DAC conference 2020 was selected to be portrayed in this selective and well-frequented library website.
View the presentation

The presentation "Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs" is now available in the IEEE CEDA presentation library.

IEEE Embedded Systems Week (ESWEEK 2020):

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

September 20-25, 2020, Prof. Teich is chairing the live Award Plenary Sessions at the Embedded Systems Week 2020. Due to the corona pandemic, the conference was held virtually this year.
more information

Members of the Organizing Committee of the 16th ACM/IEEE Embedded Systems Week (ESWEEK 2020) during an Award Plenary session of the virtual conference.

AxC´20: 5th Workshop on Approximate Computing, San Francisco, USA:

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

July 19, 2020, San Francisco: Prof. Dr.-Ing. Jürgen Teich (FAU) served as Program Co-Chair of AxC´20: 5th Workshop on Approximate Computing, co-located with DAC 2020 in San Francisco.
Nowadays, Approximate Computing (AxC) represents a novel and interesting design paradigm for building modern systems with better trade-off between efficiency, in terms of performance, power consumption, hardware area, execution timing, and the quality of the final outcomes. Indeed, AxC is based on the intuitive observation that, while performing exact computation requires a high amount of computational resources, allowing a selective approximation or an occasional relaxation of the specification may provide significant gains in energy efficiency. Suitable solutions will not be fully realized in a single layer only. Therefore, applying AxC in different layers of hardware, architecture, software and algorithms should be investigated. Moreover, while the hidden cost of AxC is a reduction of an application’s inherent resiliency to errors, AxC has also recently been demonstrated to be effective in safety-critical applications. This workshop (fifth edition after successful ones at Paderborn’15, ESWEEK’16, ETS’ 18, DATE’19) aimed at exploring AxC techniques applied at different layers, such as hardware, architecture, software and algorithms, making room for the exploration of methodologies able to exploit effective and real systems that can inspire application in many recent application domains such as machine learning, safety and security.

more information

ACM/IEEE Early Career Workshop at DAC, San Francisco, USA:

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

July 19, 2020, San Francisco: Prof. Dr.-Ing. Jürgen Teich (FAU) was panelist at the ACM/IEEE Early Career Workshop.
This workshop is for young and mid-career faculty and professionals in the fields related to electronic design automation (EDA). The workshop started in the morning with an interactive session borrowing techniques from IMPROV to help you improve your soft skills (interpersonal, communication etc.) with others. This was followed by presentations and panel discussions by professionals discussing diverse topics such as navigating the various challenges to better succeed and thrive in your academic or industry job, getting your projects funded and climbing academic and technical ladders, as well as improved cooperation between industry and academia research and development. In addition, the workshop provided rich opportunities to closely interact and network with some of the established academicians, professionals, and funding officers in EDA related fields.
more information

Prof. Dr.-Ing. Jürgen Teich (FAU) was panelist at the ACM/IEEE Early Career Workshop 2020.

57th Design Automation Conference (DAC'20), San Francisco, USA:

Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT)

Prof. Dr.-Ing. Jörg Henkel was the Technical Program Chair of the 57th Design Automation Conference (DAC'20). DAC received a record number of 984 submissions out of which 228 were selected for the technical program. For the first time DAC was held as a virtual event with a mixture of pre-recorded and live content. more information

Prof. Dr.-Ing. Jörg Henkel was the Technical Program Chair of DAC'20.

The 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2020), The University of Manchester, July 6-8, 2020:

Dr.-Ing. Frank Hannig (Hardware/Software Co-Design, FAU)

The 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2020) was hosted by The University of Manchester, from July 6 to 7, 2020. ASAP 2020 took place as an Online Conference and attracted 110 participants. The conference continued the long-standing ASAP tradition of reporting top-notch results in application-specific computer architectures and related areas.

In the welcome address, General Chair Dirk Koch (University of Manchester) and Program Co-Chair Dr.-Ing. Frank Hannig (FAU) highlighted the privilege of organizing ASAP and provided statistics on the submissions. In response to the call for papers, 118 abstract submissions with affiliations to 26 countries were received, and 87 papers went to the review process. With the help of 61 members of the Technical Program Committee, who carried out 340 reviews (about four per submission) and having intensely scrutinized the reviews, the organizers were pleased to present a high-quality technical program. The program included 21 long papers (24% acceptance rate) and 12 short papers at the online conference.

The selected papers have been divided into thematic areas (six sessions), highlighting the current research endeavors within application-specific systems, architectures, and processors. The sessions covered topics on heterogeneous computing, reconfigurable accelerators, machine learning and acceleration of neural networks, cloud computing, emerging technologies, neuromorphic computing, edge computing, approximate computing, and computer arithmetic. The strong technical program was complemented by two keynote talks on: “An Overview of High Performance Computing and Using Mixed Precision in Numerical Computations to Speedup Linear Algebra Solvers” by Jack Dongarra, University of Tennessee and Oak Ridge National Laboratory, USA; and “Formally Verifying Hardware for Secure and Private Computing” by Satnam Singh, Google Research, USA.

Program Co-Chair Dr.-Ing. Frank Hannig (left). Socializing at the "After-ASAP Drink" (right).

Since networking and social aspects are often neglected at online conferences, there was an “After-ASAP Drink” at the end of the event. Here, everybody had his or her favorite drink ready for a video toast and online chat.

Best Paper Award at VDAT 2020, Bhubaneswar, India, July 2-4, 2020

T.K.R. Arvind, Marcel Brand, Christian Heidorn, Srinivas Boppu, Dr.-Ing. Frank Hannig and Prof. Dr.-Ing. Jürgen Teich

The paper "Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats" presented at the 24th International Symposium on VLSI Design and Test (VDAT 2020) in Bhubaneswar, India won the Best Paper Award.

8th ACM Workshop on Information Hiding and Multimedia Security, June 22-25, 2020:

Franziska Schirrmacher (FAU)

Franziska Schirrmacher and Christian Riess (FAU) served as General Chairs of the ACM Workshop on Information Hiding and Multimedia Security. The workshop is well known in the multimedia security community and covers information hiding topics, such as watermarking, steganography, steganalysis, and covert channels. Multimedia identification and biometrics, just to name a few of the multimedia security topics, are also addressed in the workshop. The event was held as a virtual conference with a mixture of pre-recorded and live content.

Participants of the virtual ACM Workshop on Information Hiding and Multimedia Security 2020.

Detecting the Gender Gap in Computer Science — A Bibliometric Approach, May, 2020:

Dr. Sandra Mattauch (FAU), Dr. Katja Lohmann (Leibniz Universität Hannover), Dr.-Ing. Frank Hannig (FAU), Prof. Dr.-Ing. Daniel Lohmann (Leibniz Universität Hannover) and Prof. Dr.-Ing. Jürgen Teich (FAU)

Our manuscript entitled "Detecting the Gender Gap in Computer Science — A Bibliometric Approach" is published in Communications of the ACM.

The low share of women in computer science is documented by many surveys. Most of these studies are based on registrations or enrolments of universities or other scientific institutions. In this paper, we present an approach to a) detect the gender gap in the group of scientists that are currently active in research and b) classify differences for different fields of computer science. This group comprises professors, industrial researchers, senior lecturers, postdoctoral researchers, and doctoral students shortly before finishing their theses. The proportion of women in a specific scientific area of computer science might provide valuable information for strategies to recruit women as postdocs or professors.

Read the paper.
Press release FAU

Dr. Sandra Mattauch and Dr. Katja Lohmann were interviewed about their study on Detecting the Gender Gap in Computer Science — A Bibliometric Approach.

PhD Forum Best Poster Prize at DATE 2020, March 9, 2020:

Behnaz Pourmohseni (Hardware/Software Co-Design, FAU)

Behnaz Pourmohseni received the PhD Forum Best Poster Prize at DATE 2020 for her poster titled "System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems". The prize is supported by EDAA, ACM Sigda and IEEE CEDA. Due to the Covid-19 pandemic the DATE conference was held virtually.

Behnaz Pourmohseni receiving the PhD Forum Best Poster Prize at DATE 2020.

Dagstuhl Seminar 20081 "Scheduling", Schloss Dagstuhl, February 16-21, 2020:

Prof. Dr. Nicole Megow (UB), David Shmoys (Cornell University, USA) and Ola Svensson (EPFL, Switzerland)

Scheduling is a major research field that is studied from a practical and theoretical perspective in computer science, mathematical optimization, and operations research. Applications range from traditional production scheduling and project planning to the newly arising resource management tasks in the advent of internet technology and shared resources. Despite the remarkable progress on algorithmic theory for fundamental scheduling problems, new questions gain greater prominence due to the rise of new applications.

Participants of the Dagstuhl Seminar 20081 "Scheduling" February 16-21, 2020.

This Dagstuhl Seminar focused on the interplay between scheduling problems and problems that arise in the management of transportation and traffic. There are several notable aspects of the scheduling problems that arise particularly in this context:
1. the role of dynamic decision-making in which data-driven approaches emerge (especially those that have stochastic elements in modeling the multi-stage decision-making);
2. the interplay between scheduling aspects and what might be viewed as routing aspects, providing a spacial component to the nature of the scheduling problem;
3. the tension between questions of coordination and competition that arise from the fact that for many of the issues in this domain, there are significant questions that depend on the extent to which the traffic can be centrally coordinated.
Since the community working on the intersection of scheduling and traffic is itself rather broad, we methodologically focus on the theoretical design of algorithms, mathematical optimization methods, and the interplay between optimization and game-theoretic approaches.

more information

Invasic Computing at HiPEAC Computer Systems Week 2020, Bologna, January 21, 2020:

Invited Talk, HiPEAC Computer Systems Week 2020: Tackling the MPSoC Data Locality Challenge for Distributed-Shared Memory Architectures

Prof. Dr. Andreas Herkersdorf (Chair of Integrated Systems, TUM)

Prof. Herkersdorf gave an invited talk within the PARMA-DITAM: Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms at HiPEAC Computer Systems Week 2020.

Data access latencies and bandwidth bottlenecks frequently represent major limiting factors for the computational effectiveness of multi- and many-core processor architectures. This talk introduces two conceptually complementary approaches to reduce the synchronization overheads for coherence maintenance and to improve the locality between computing resources and data: Region-based cache coherence and near memory acceleration. The presented approaches represent current work in the DFG Transregional Collaborative Research Center “Invasive Computing”. A 2D array of compute tiles with multiple, heterogeneous RISC cores, two levels of caches and a tile-local SRAM memory serves as reference processing platform. Compute tiles, I/O tiles and globally shared DDR SDRAM memory tiles are interconnected by a meshed Network on Chip (NoC) with support form multiple quality of service levels. Overall, this processing architecture follows a distributed-shared-memory model. The limited degree of parallelism in many embedded computing applications also bounds the number of compute tiles possibly sharing associated data structures. Therefore, we envision region-based cache coherence (RBCC) among a limited working set of compute tiles over global coherence approaches. Coherence regions can dynamically be reconfigured at run time and comprise a number of arbitrary (adjacent or non-adjacent) compute tiles which are interconnected through regular NoC channels for the exchange of coherency protocol messages. We will show that region-based coherence allows maintaining substantially smaller coherence directories(e.g., by approx. 40% reduced in size for 16 tiles systems with up to 4 tiles per region) and shorter sharer checking latencies than global coherence. Near memory processing is an alternative concept to increase data/task locality by means of near memory accelerators (NMA). NMA positions processing resources for specific forms of data manipulations as close as possible to the data memory. The evident benefits are: reducing global interconnect usage,shortening of access latencies and, thus, increasing compute efficiency. In distributed-shared-memory architectures, where accelerator units can be affiliated with different tile-local SRAMs as well as with the globally shared DDRSDRAM, near memory acceleration requires thorough consideration of task mapping as well as task and data migration into and among compute tiles.

more information

Invited Talk, HiPEAC Computer Systems Week: Secure hardware composition: starting from the root of trust

Prof. Dr. Ingrid Verbauwhede (KU Leuven, BE)

Prof. Verbauwhede gave an invited talk within the PSeHAS: Workshop on Secure Hardware, Architectures, and Operating Systems at HiPEAC Computer Systems Week 2020. What is “hardware” security? The network designer relies on the security of the router box. The software developer relies on the TPM (Trusted Platform Module). A system designer assume that cryptographic keys, random initial values, nonces, freshness, hardware isolation, or secure storage is available. At the same time, electronics shrink: sensor nodes, IOT devics, smart devices are becoming more and more available. Adding security and cryptography to these often very resource constraint devices is a challenge. This presentation will focus on how to create secure platforms from the bottom-up, starting from the roots of trust.

more information

At the HiPEAC Computer Systems Week Prof. Verbauwhede was also invited to give an interview. She sets out why hardware needs to be secure by design, with some alarming examples of what can happen if security is poorly implemented. She explains why there should be more guarantees of security in products and why Europe should build on its leading position in this field.

video

Workshop on the Computing Continuum at HiPEAC Computer Systems Week 2020:

Prof. Dr. Michael Gerndt, Prof. Dr.-Ing. Walter Stechele (TUM) and Sven Karlsson (Ericsson)

Computing Continuum Workshop at HiPEAC (photographs HiPEAC 2020).

The HiPEAC Computer Systems Week took place in Bologna, Italy on January 20, 2020.
The face of computing has changed dramatically in recent years. A large variety of devices such as simple sensors and microcontrollers, edge computers, mobile devices, laptops, servers, clusters, and HPC systems build a ubiquitous infrastructure, called the Computing Continuum. Many of today’s applications from areas such as industrial production (Industry 4.0), social networks, precision medicine and large scientific experiments require a dynamically varying amount of compute and storage capacity for gathering and processing large data sets to form the basis for advanced services. The need for dynamics is due to changes in the data rates, the services request rates, as well as the delivery process. The resources of the continuum are typically shared among different tenants and applications. Sharing resources is, for example, the driving force in today’s cloud offerings and their extensions into distributed infrastructures in the form of edge and fog computing as well as the mobile extensions based on radio networks. Efficient sharing requires dynamic and data- and application-aware scheduling of tasks onto the available resources. Further, careful resource management and resource isolation is used to enable performance guarantees. This is especially important in HPC and embedded computing. Sharing reduces over-provisioning but requires careful dynamic management of shared resources, including on-chip communication, memory hierarchy, and power.

This workshop had the goal to gather application scenarios as well as resource management technologies for the Computing Continuum. Topics to be covered included:

• Distributed scientific, social, web, IoT, and enterprise applications
• Application architecture models such as workflows, microservices, function-as-a-service, and cloud native applications, streaming applications
• Concepts for resource aware programming
• Application characterization and performance modeling
• Dynamic application tuning for performance and energy
• Smart orchestration and self-adaptive resource provisioning
• Horizontal and vertical auto-scaling across cloud and edge
• Operating system concepts such as uni-kernel
• Computer systems and computer architectures for the compute continuum
• Communication models

more information

Talks from Young Scientists and Doctoral Researchers at HiPEAC Computer Systems Week 2020:

Dr. Bertrand Simon (UB), Jophin John (TUM), Florian Schmaus and Behnaz Pourmohseni (FAU)

Dr. Bertrand Simon (left) and Behnaz Pourmohseni (right) at HiPEAC.

At HiPEAC Computer Systems Week 2020 our young scientists gave talks on their current work. Florian Schmaus talked about "Towards Taming the Computing Continuum: System Software for Future Many-Core Architectures" and Dr. Bertrand Simon about "Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice". Behnaz Pourmohseni presented her work on "Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems". Jophin John gave a talk on "Dynamic Resource Management on HPC Systems to enable integration into the Computing Continuum."

Events 2019

VDE Award 2019, Munich, November 24, 2019

Nael Fasfous (Integrated Systems, TUM)

Nael Fasfous from TUM has been awarded the VDE Award 2019, in recognition of his Master Thesis on the topic of "Compact Directories with Hybrid Architecture Aware Eviction Policies for Distributed Shared Memory MPSoCs". In his thesis, Nael proposed innovative cache eviction strategies for Multiprocessor System-on-Chip architectures. Within Project B5, Akshay Srivatsa was the advisor of this thesis. The VDE Award has been given to Nael Fasfous from the Association of German Engineers (Verein Deutscher Ingenieure, VDE Südbayern) on November 24, 2019. more information

Nael Fasfous (Integrated Systems, TUM) has been awarded the VDE Award 2019.

Keynote Talk, 26th ACM Conference on Computer and Communications Security in London, UK, November 11-15, 2019: The Need for Hardware Roots of Trust

Prof. Dr. Ingrid Verbauwhede (KU Leuven, BE)

Prof. Verbauwhede (KU Leuven, BE) gave a talk on "The Need for Hardware Roots of Trust" at the 26th ACM Conference on Computer and Communications Security in London.

Electronics are shrinking and penetrating all aspects of our lives. IOT devices fill our homes, cars are driving autonomously, body area networks monitor our health. Adding security and cryptography to these often very resource constraint devices is a challenge. We would like the solutions to be lightweight and at the same time resistant to remote as well as local physical manipulation attacks.Software and cryptographic security protocols rely on hardware roots of trust. Protocol designers assume that cryptographic keys, random initial values, nonces, freshness, hardware isolation, or secure storage is simply available to them. This presentation focused design methods for hardware roots of trust in general and more specifically on Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNG), two essential roots of trust.

Invited Talk, Kolkom 2019, University of Paderborn, November 7-9, 2019: A Combinatorial optimization with explorable uncertainty

Prof. Dr. Nicole Megow (UB)

Prof. Megow gave an invited talk on "A Combinatorial optimization with explorable uncertainty" at the Colloquium on Combinatorics (Kolkom 2019) at University of Paderborn.

In the traditional frameworks for optimization under uncertainty, an algorithm has to accept the in-completeness of input data. Clearly, more information or even knowing the exact data would allow for significantly improved solutions. How much more information suffices for obtaining a certain solution quality? Which information shall be retrieved? Explorable uncertainty is a recently proposed framework in which parts of the input data are initially unknown, but can be obtained at a certain cost using queries. An algorithm can make queries one by one until it has obtained sufficient information to solve a given problem. The challenge lies in balancing the cost for querying and the impact on the solution quality. In this talk, we give a short overview on recent work on explorable uncertainty for combinatorial optimization problems, focussing on the minimum spanning tree problem and a scheduling problem.

Kolkom 2019 - Invited speakers and organizers.

LZE Tech Day, Erlangen, November 7, 2019:

The Leistungszentrum Elektroniksysteme (LZE) is a joint initiative of the Fraunhofer-Gesellschaft, its Institutes IIS and IISB and the Friedrich-Alexander-University Erlangen-Nürnberg (FAU), together with other non-university research institutions and associated industrial partners. The LZE is breaking new ground here. With novel structures and cooperation models between science and industry, the successful transfer of research results has been initiated.

Impressions from the LZE Tech Day 2019.

At the LZE Tech Day, examples from different stages of the innovation chain were shown ranging from new wide-range wireless communication technology as a best practice for comprehensive, successful market development, to completed research projects that are in the early stages of exploitation, to technological development that is just beginning. We presented an invasive parallel Shallow Water application demonstration to raise awareness for the research work of the Transregio 89.

more information

Keynote Talk, NorCAS 2019, Helsinki, October 29, 2019:
Tackling the MPSoC Data Locality Challenge with Regional Coherence and Near Memory Acceleration

Prof. Dr. Andreas Herkersdorf (Chair of Integrated Systems, TUM)

Prof. Dr. Andreas Herkersdorf presented major results of our work done within project B5 at the IEEE Nordic Circuits and Systems Conference (NorCAS) 2019 in Helsinki.
Data access latencies and bandwidth bottlenecks frequently represent major limiting factors for the computational effectiveness of multi- and many-core processor architectures. This keynote talk introduced two conceptually complementary approaches to reduce the synchronization overheads for coherence maintenance and to improve the locality between computing resources and data: Region-based cache coherence and near memory acceleration.

A 2D array of compute tiles with multiple, heterogeneous RISC cores, two levels of caches and a tile-local SRAM memory serves as reference processing platform. Compute tiles, I/O tiles and globally shared DDR SDRAM memory tiles are interconnected by a meshed Network on Chip (NoC) with support for multiple quality of service levels. Overall, this processing architecture follows a distributed-shared-memory model. The limited degree of parallelism in many embedded computing applications also bounds the number of compute tiles possibly sharing associated data structures. Therefore, we envision region-based cache coherence (RBCC) among a limited working set of compute tiles over global coherence approaches. Coherence regions can dynamically be reconfigured at runtime and comprise a number of arbitrary (adjacent or non-adjacent) compute tiles which are interconnected through regular NoC channels for the exchange of coherency protocol messages. We showed that region-based coherence allows maintaining substantially smaller coherence directories (e.g., by approx. 40% reduced in size for 16 tiles systems with up to 4 tiles per region) and shorter sharer checking latencies than global coherence.

Near memory processing is an alternative concept to increase data/task locality by means of near memory accelerators (NMA). NMA positions processing resources for specific forms of data manipulations as close as possible to the data memory. The evident benefits are: reducing global interconnect usage, shortening of access latencies and, thus, increasing compute efficiency. In distributed-shared-memory architectures, where accelerator units can be affiliated with different tile-local SRAMs as well as with the globally shared DDR SDRAM, near memory acceleration requires thorough consideration of task mapping as well as task and data migration into and among compute tiles.

more information

Invited Talk, AI College of National Chiao Tung University in Tainan, Taiwan, October 23, 2019: Novel Ideas in Timing of Digital Circuits

Prof. Dr.-Ing. Ulf Schlichtmann (Chair of Electronic Design Automation, TUM)

Prof. Dr.-Ing. Ulf Schlichtmann visited Prof. Mark Po-Hung Lin at the AI College of National Chiao Tung University in Tainan, Taiwan. He gave a talk on "Novel Ideas in Timing of Digital Circuits" which included signficant research contents on Invasive Computing. Prof. Lin’s students engaged in discussion and gave creative suggestions. One researcher is so excited that she wants to visit TUM now.

The photo shows Ulf Schlichtmann with his host, Prof. Mark Po-Hung Lin, and his students together with another visitor.

Invasive Computing at the "Lange Nacht der Wissenschaften", Erlangen, October 19, 2019:

Every other year, the Long Night of the Sciences electrifies the metropolian region around Nuremberg, Fürth and Erlangen. This kind of event is the biggest in Germany with around 20,000 visitors. Researchers take this terrific possibility to showcase their research work to the broad audience. Also we took the chance to present the Transregio 89 (Invasive Computing).

Impressions from the Long Night of Sciences 2019 at FAU.

On one hand, we demonstrated research on real-time multicore computing to visitors who are already familiar with Computer Science. In turn, the demonstrations opened up for interesting discussions about the characteristics of invasive computing. On the other hand, we introduced "InvasiTrax", a game based on the GraviTrax construction kit being very popular among children as a perfect way to explain invasive computing to people who have never heard of it before. Interactively visitors experience the differences between a "normal" multicore system and a system built upon invasive computing. InvasiTrax was particularly well received by children. We are very pleased that also a lot of girls came around to get to know InvasiTrax and learn something about invasive computing. Maybe we could contribute to more female students deciding for a STEM study program in the future. Moreover, our self-made movie "InvasIC for Dummies" (see https://www.youtube.com/watch?v=4kOQYHhnZW0) was shown, adding a touch of multimedia to our presentation. Furthermore, we portrayed general information about the Transregio at a poster. All in all, we are very satisfied with the Long Night of the Sciences 2019. We have been able to introduce invasive computing to a large number of visitors enlarging the comprehension for this young research field and raise awareness for Computer Science in general.

more information

Invited Talk, University of Otago, October 4, 2019: Adaptive Memory Protection for Many-core Systems

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat gave an invited talk at the University of Otago, New Zealand on "Adaptive Memory Protection for Many-core Systems".

Hardware-based memory protection is widely applied in all areas of computing, it is a fundamental building block for safety and security. However, improving protection measures by means of dedicated hardware such as a memory management unit (MMU) is not carved in stone, but rather depends on the application domain and the facts of the programming system and hardware, respectively.
State of the art operating systems statically determine whether or not software entities are subject to memory protection. If enabled, costly operations will follow due to multi-level page-table handling, TLB (translation look-aside buffer) invalidations, and the release of inter-processor interrupts. This all reduces performance, increases operating-system noise, and makes system behavior unpredictable. If application programs are type-safe, then enabled hardware protection becomes a pretty much superfluous features. Contrariwise, if the programs are type-unsafe, disabled hardware protection opens door and gate for malware.
This talk was on adaptive memory-protection that is capable of dynamically changing the per-program protection state. The feature is triggered at load/unload time of application programs and applies in the background of running processes. Measurement results were presented and discussed in terms of timing predictability of the system.

Invited Talk, University of Wellington, September 23, 2019: Predictability Issues in Operating Systems: Time, Space, Energy

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat and Dr.-Ing. Timo Hönig (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat and Dr.-Ing. Timo Hönig gave an invited talk at the Victoria University of Wellington, New Zealand on "Predictability Issues in Operating Systems: Time, Space, Energy".

Predictability is always subject to the underlying assumptions being made. For real-time systems, time response of processes in relation to the strictness of deadlines is of particular importance. With an additional focus on embedded systems, space and energy requirements become relevant as well and need to be considered in combination. As far as software is concerned, structure and organisation of the programs to be executed determines whether or not predictable processes will take place in a given computing system. Design for predictability is an overarching aspect that crosscuts the whole computing system and particularly addresses operating systems.
This talk was about structuring principles of non-sequential programs - in the shape of but not limited to operating systems - to abet predetermination of quality attributes of non-sequential (real-time) processes, it was not about analytical methods to effectively predetermine these attributes. Issues in operating systems as to timing, space, and energy requirement were touched. Emphasis thereby was on coordination of cooperation and competition between processes, namely synchronisation. It was shown how measures of process synchronisation against the background of many-core processors cater to these issues.

Invited Talk, Workshop on Robust Optimiziation, University of Siegen, September 19-20, 2019: Optimization with Explorable Uncertainty

Prof. Dr. Nicole Megow (UB)

Prof. Megow gave an invited talk on "Optimization with Explorable Uncertainty" at the Workshop on Robust Optimiziation at the University of Siegen.

Explorable uncertainty refers to settings where parts of the input data are initially unknown, but can be obtained at a certain cost using queries. An algorithm can make queries one by one until it has obtained sufficient information to solve a given problem. The challenge lies in balancing the cost for querying and the impact on the solution quality. In this talk, we give a short overview on recent workon explorable uncertainty for combinatorial optimization problems, mention work on the minimumspanning tree problem, and then focus on a new scheduling problem.

Workshop on Robust Optimiziation, University of Siegen

New Zealand-Germany Research Workshop, University of Auckland, September 16, 2019:

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat and Dr.-Ing. Timo Hönig (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat and Dr.-Ing. Timo Hönig organised in cooperation with Prof. Dr. Zoran Salcic, Dr. Morteza Biglari-Abhari and Dr. Avinash Malik (UOA) a workshop on "Time predictability, energy awareness and security in embedded and real-time systems".

Penetration of embedded systems into all walks of our lives and domains of business activity, exemplified with the rise of Internet of Things, raises attention to many performance criteria for underlying systems and applications that are typically considered independent each of the other. Examples are timing predictability of execution, energy consumption awareness and security, to name a few. The workshop will centre on these issues and seek for synergies of research where more than one key performance parameters are targeted. System-level approaches and solutions were presented and discussed, as well as their implementations in real-world applications. The workshop included a number of invited participants and it was open for attendance to the other academic staff and research students from Department of Electrical, Computer and Software Engineering (ECSE) on first come first registered basis.

1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Canmore (Banff Area), September 3-4, 2019:

Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT) and Prof. Dr.-Ing. Ulf Schlichtmann (Chair of Electronic Design Automation, TUM)

This workshop focused on Machine Learning (ML) methods for all aspects of CAD and electronic system design. The predecessor of this workshop was held at the Design, Automation and Test in Europe (DATE) Conference in March 2019. The workshop was sponsored by both IEEE Council on Electronic Design Automation (CEDA) and ACM Special Interest Group on Design Automation (SIGDA).
more information

Summer of Integration, August 7, TUM, 2019:

On the 7th of August researchers from different projects met for two days at TUM for their annual "Summer of Integration". This years meeting was dedicated to the joint improvement of the prototyping system and its infrastructure.

Invited Talk, International Symposium on Low Power Electronics and Design (ISLPED 2019), July 31, 2019:
NCFET-Aware Voltage Scaling

Sami Salamin, Martin Rapp, Hussam Amrouch, Girish Pahwa, Yogesh Chauhan and Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT)

more information

B2Run, Nuremberg, July 23, 2019:
Run for Fun

"Run for Fun" was the theme under which our team participated at this year's B2Run in Nuremberg in July. The B2Run is a company racing series that is held at 17 locations in Germany. In Nuremberg the course leads around the great and the small Dutzendteich with the finish in the Max-Morlock-Stadium. Despite the very hot weather conditions all ten runners reached the finish of the almost 6 km long running track and enjoyed the great atmosphere. Inspired by the cheering spectators, the team proved that they can achieve a great deal together, whether on the PC, in the lab or in sports.
Announcement on the FAU Homepage
Announcement on Facebook

InvasIC-Runners at the B2Run 2019

Best Paper Award at SAMOS XIX Conference, Samos Island, Greece, July 11, 2019

Akshay Srivatsa, Sven Rheindt, Dirk Gabriel, Dr.-Ing. Thomas Wild and Prof. Dr. Andreas Herkersdorf (Chair of Integrated Systems, TUM)

The paper "CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-based Manycore Architectures" presented at this year's SAMOS Conference (International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation) received the best paper award.

In addition to this great success it is also worth noting that a second paper from the TRR 89 was a strong competitor and ended up on second position. "SHARQ: Software-Defined Hardware-Managed Queues for Tile-based Manycore Architectures" was written by Sven Rheindt, Sebastian Maier, Florian Schmaus, Dr.-Ing. Thomas Wild, Prof. Dr.-Ing. Wolfgang Schröder-Preikschat and Prof. Dr. Andreas Herkersdorf. The SAMOS Conference is annually taking place on the Samos Island, Greece. This years edition took place from July 7 to 11.

Invited Talks, Technische Universität Dortmund, July 4/5, 2019:
Workshop on Embedded Systems, Dedicated to Peter Marwedel´s 70th Birthday

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU) and Prof. Dr. Andreas Herkersdorf (Chair of Integrated Systems, TUM)

Prof. Teich gave a talk about "Run-Time Enforcement of Non-functional Program Properties on MPSoCs". Prof. Herkersdorf talked about "As Embedded Systems Became Serious Grown-Ups, They Decide on Their Own".
more information

Invited Talk, 9th International Workshop on Runtime and Operating Systems for Supercomputers (ROSS 2019), June 25, 2019:
Asynchronous Abstract Machines: Anti-noise System Software for Many-core Processors

Sebastian Maier, Dr.-Ing. Timo Hönig, Peter Wägemann and Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Dr.-Ing. Timo Hönig held a talk on the paper "Asynchronous Abstract Machines: Anti-noise System Software for Many-core Processors".

Today's systems offer an increasing number of processor cores, however, the chance to operate them efficiently by dedicating cores to specific tasks is often missed. Instead, mixed workloads are processed by each core which leads to system noise (i.e., interferences, scheduling overheads) and yields subpar performance, only. We therefore propose a system design based on Asynchronous Abstract Machines (AAMs). An AAM features a light-weight scheduler and is dedicated to a specific group of tasks with common characteristics (i.e., shared code and data). It offers an asynchronous, task-based interface for efficient interaction between AAMs. Just like applications are built from AAMs, even the OS itself consists of AAMs that are interfaced by applications via asynchronous messages instead of synchronous system calls. A dedicated OS component, which is aware of all AAMs in the system, is responsible for dynamic and exclusive allocation of cores to AAMs depending on their current workload. Thus, cores rarely switch between heterogeneous workloads of different AAMs. And, at the same time, frequent switches between homogeneous tasks become fast, local operations of an AAM, which do not involve the OS kernel. In this paper, we describe shortcomings of existing operating systems, our new system design concept, and present evaluation results of our prototype implementation..
slides

Invited Talk, Xidian University, June 21/22, 2019:
Machine Learning Approaches for Efficient Design Space Exploration of Application-specific NoCs

Prof. Dr.-Ing. Ulf Schlichtmann and Dr.-Ing. Li Zhang (Chair of Electronic Design Automation, TUM)

The photo shows Li Zhang and Ulf Schlichtmann together with Prof. Yintang Yang, Vice President of Xidian University, with some of his colleagues.

Dr.-Ing. Li Zhang and Prof. Ulf Schlichtmann (TUM) visited Xidian University in Xi’an, China on June 21/22, 2019, for discussions about research collaborations. On June 22, Prof. Schlichtmann gave an overview on the research of the TUM’s Chair for Electronic Design Automation – which of course includes the InvasIC research – as well as a dedicated talk on "Machine Learning Approaches for Efficient Design Space Exploration of Application-specific NoCs". Despite the talk happening on a Saturday, it was attended by more than 125 participants. The talk was followed by a very lively discussion. Dr. Li Zhang had already visited Xidian University earlier in January 2019 and given a talk on her timing-related research which she performed in the context of TRR 89.

Keynote Talk, ARCS 2019, May 20-23, 2019
Predictability Issues in Operating Systems

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat gave an invited keynote talk at the 32nd International Conference on Architecture of Computing Systems (ARCS 2019) in Copenhagen, Denmark.
Predictability is always subject to the underlying assumptions being made. For real-time systems, time response of processes in relation to the strictness of deadlines is of particular importance. With an additional focus on embedded systems, space and energy requirements become relevant as well and need to be considered in combination. As far as software is concerned, structure and organisation of the programs to be executed determines whether or not predictable processes will take place in a given computing system. Design for predictability is an overarching aspect that crosscuts the whole computing system and particularly addresses operating systems.
This talk was about structuring principles of non-sequential programs - in the shape of but not limited to operating systems - to abet predetermination of quality attributes of non-sequential (real-time) processes, it is not about analytical methods to effectively predetermine these attributes. Issues in operating systems as to timing, space, and energy requirement are touched. Emphasis thereby is on coordination of cooperation and competition between processes, namely synchronisation. It is shown how measures of process synchronisation against the background of many-core processors cater to these issues.
more information

Invited Talk, ACM International Conference on Computing Frontiers 2019, April 30, 2019:
Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic

Marcel Brand, Michael Witterauf, PD Dr.-Ing. Frank Hannig and Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Marcel Brand held a talk on the paper "Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic".

Many embedded applications strive for high performance and power efficiency but rely on latency-intensive floating-point operations. This expensiveness can be offset, for example, by approximate and mixed-precision floating-point computation. In this paper, we present a novel concept called anytime instructions. Anytime instructions explicitly specify the number of result bits that are calculated at full precision. After presenting the basics of anytime instructions, we apply this novel concept to floating-point division by presenting an anytime division functional unit that is implemented in a VLIW processor. In this setup, we show the effectiveness of anytime instructions in iterative computations. We show a latency improvement of 54.8 % for computing 53 iterations of the Babylonian method for square-root calculation while not sacrificing the accuracy of the final square-root result.
more information

Inaugural lecture: "(Viel-)Kern-Vielfalt hilft viel – aber wie?"

April 26, 2019, Erlangen (FAU): PD Dr.-Ing. Frank Hannig (FAU) will give his inaugural lecture on "(Viel-)Kern-Vielfalt hilft viel – aber wie?" at "Tag der Informatik".
more information

Best Presentation Award April 19, 2019, Montreal, Canada:

Simon Schuster (FAU)

Simon Schuster received the Best Presentation Award for his presentation on the paper "Proving Real-Time Capability of Generic Operating Systems by System-Aware Timing Analysis" contributed by Simon Schuster, Peter Wägemann, Peter Ulbrich, and Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (FAU) at RTAS 2019.
more information

Invited Talk, The University of Tokyo, April 18, 2019:
Multi-Core Computing with Timing, Reliability, and Security Guarantees

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

In this talk, we gave an overview of novel techniques for systematically mapping applications to NoC-based multi-core architectures (MPSoCs). Complex applications requiring heterogenous processing resources are often described by task graphs with data dependencies. Here, the nodes represent actors or tasks which are typically activated periodically based on the availability of data. One prominent domain of applications fitting this model is stream processing. Here, it is often important to guarantee either bandwidth or execution time requirements. But more recently, also security, energy and reliability aspects impose constraints on the mapping of the tasks as well as their communication to cores, respectively routes in the underlying NoC.
In the context of mapping methodologies, we first present a class of algorithms that perform "Self-Embedding". The idea is here that a source node issues a request to find appropriate resources to embed its sucessor tasks, and so on. The next class of techniques introduced is called "Hybrid Application Mapping (HAM)". Here, a careful analysis and characterization of symmetric mappings by constellations of cores and routes is explored in a static (compile-time) phase called "Design Space Exploration (DSE)". At run-time, the operating system then only needs to search within such pre-analysed constellations for finding a concrete mapping that will satisfy the given non-functional constraints by construction. We presented ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that deadlines or throughput requirements will be automatically met for streaming applications. Finally, we concluded with a discussion on resource constellations that may satisfy certain security requirements on an MPSoC.

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU) visited the University of Tokyo and gave an invited talk at the department of creative informatics.

Invited Talk, International Symposium on Applied Reconfigurable Computing (ARC 2019), April 10, 2019:
Hybrid Prototyping for Manycore Design and Validation

Leonard Masing, Fabian Lesniak and Prof. Dr.-Ing. Jürgen Becker (ITIV, KIT)

The trend towards more parallelism in information processing is unbroken. Manycore architectures provide both massive parallelism and flexibility, yet they raise the level of complexity in design and programming. Prototyping of such architectures helps in handling this complexity by evaluating the design space and discovering design errors. Several system simulators exist but they can only be used for early software development and interface specification. FPGA-based prototypes on the other hand are restricted by available FPGA resources or expensive multi-FPGA prototyping platforms. We present a hybrid prototyping approach for manycore systems that consists of an FPGA-part and a virtual part of the architecture on a host system. The hybrid prototyping requires less FPGA resources while retaining its speed advantage and enabling flexible modeling in the virtual platform. We describe the concept, provide an analysis of timing accuracy and synchronization of the FPGA with the Virtual Platform (VP) and show an example in which the hybrid prototype is used for feature development and evaluation of a scientific manycore architecture. The hybrid prototype allows us to evaluate a 7x7 architecture on a Virtex-7 XC7VX485T FPGA board which otherwise could only fit a reduced 2x2 design of our architecture.
more information

Design, Automation and Test in Europe (DATE) 2019, March 25-29, 2019:

DATE combines the world’s favourite electronic systems design and test conference with an international exhibition for electronic design, automation and test, from system-level hardware and software implementation right down to integrated circuit design. It took place at the Firenze Fiera in Florence, Italy from 25 to 29 March 2019.
The DATE 2019 Conference and Exhibition attracted more than 1,600 registrations from over 40 countries and concluded with excellent feedback from both participants and exhibitors.

Impressions from DATE 2019. (photographs DATE 2019 / © Cruz Garcia)

On Monday, the DATE week started with five in-depth technical tutorials on the main topics of DATE as well as a hands-on industry tutorial given by leading experts in their respective fields. The topics covered Machine Learning for Manufacturing and Test, OpenCL Design Flows for FPGAs, Approximate Computing, Hardware-based Security, and Safety and Security in Automotive, while the hands-on tutorial was on Quantum Computing with IBM Q and Qiskit.
Prof. Jürgen Teich had the honour to be General Chair of DATE 2019 and opened the conference on Tuesday. During the Opening Ceremony, plenary keynote lectures were given by Astrid Elbe, Managing Director of Intel Labs Europe, and Jürgen Bortolazzi, Director Driver Assistance Systems and Highly Automated Driving at Porsche. Furthermore, a talk by Claudio Giorgione, Curator of the Leonardo Department at the National Museum of Science and Technology Milano, gave insight into life and work of Leonardo da Vinci in line with the 500th anniversary of his death, which is celebrated in Florence in 2019.

Impressions from DATE 2019. (photographs DATE 2019 / © Cruz Garcia)

The main conference programme from Tuesday to Thursday included 58 technical sessions organized in parallel tracks from the four areas
D – Design Methods & Tools
A – Application Design
T – Test and Dependability
E – Embedded and Cyber-physical Systems
and from several special sessions on Hot Topics, such as Emerging Design Technologies, Design and Test of Secure Systems, IoT Security, Embedded Systems for Deep Learning, Augmented Living and Personalized Healthcare, Robotics and Industry 4.0, as well as results and lessons learned from European projects.
Two Special Days in the programme focused on areas bringing new challenges to the system design community. On Wednesday, the keynote on the topic of heterogeneous, high-scale computing in the era of cloud-connected devices by David Pellerin, Amazon US, was the highlight of the special day on “Embedded Meets Hyperscale and HPC”. During the Special Day on “Model-Based Design of Intelligent Systems” on Thursday, Edward Lee from UC Berkeley took “A Fundamental Look at Models and Intelligence” in his keynote.

Impressions from DATE 2019. (photographs DATE 2019 / © Cruz Garcia)

One of the highlights of the DATE week was the DATE Party and took place in the Palazzo Borghese, which is located in the heart of Firenze and is a beautiful example of neoclassic architecture. Local delights, entertaining music and a visit by Leonardo da Vinci made this evening a memorable event on its own!

Further impressions from DATE 2019. (photographs DATE 2019 / © Cruz Garcia)

On Friday, 10 full-day workshops covered several hot topics from areas like (a) Open Source and Machine Learning in EDA, (b) Emerging Techniques for Memories, Interconnections, and Quantum Computing, (c) Hardware Design, Synthesis, and Approximate Computing, as well as EDA in application domains such as (d) Autonomous Systems and IoT. Furthermore, an International F1/10 Autonomous Racing Demo took place, supported by IEEE CEDA. This presentation of open-source, affordable and high-performance 1/10 scale autonomous vehicles was a particular highlight on the last day of DATE 2019.
more information

Exhibition Theatre Session at DATE 2019, March 25-29, 2019:

Prof. Dr.-Ing. Jürgen Teich, General Chair of DATE 2019 organised an Exhibition Theatre Session on “DFG Collaborative Funding Instruments” on 26 March with an associated exhibition of selected currently funded collaborative research initiatives which ran for three days (Tuesday – Thursday).
The session was chaired by German Research Foundation (DFG) program director Dr. Andreas Raabe who started with an introduction of which types of collaborative funding instruments are offered in Germany, but also funding opportunities for international cooperations. After this introduction, concrete initiatives in the scope of topics of DATE were shortly introduced and summarized by representatives with a majority of these initiatives also exhibiting during the conference week. Two Priority Programs (SPP1648 Software for Exascale Computing and SPP2037 Scalable Data Management for Future Hardware), three Collaborative Research Centres (SFB 901 On-the-fly Computing, SFB 912 Highly Adaptive Energy Efficient Computing and SFB 876 Providing Information by Resource-Constrained Data Analysis) and the Transregional Research Centre TRR 89 Invasive Computing, as well as the Research Unit FOR 1800 (Controlling Concurrent Change – Towards Self-Aware Automotive And Space Vehicles) and a Bi-National Research Project (Conquering MPSOC Complexity with Principles of a Self-Aware Information) used the opportunity to present newest ideas, work-in-progress and lessons learned from the project.

Impressions from the Exhibition Theatre Session at DATE 2019. (photographs DATE 2019 / © Cruz Garcia)

Prof. Dr.-Ing. Jürgen Teich Awarded at DATE 2019, March 25-29, 2019:

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Dr.-Ing. Jürgen Teich was honoured with the IEEE CS TTTC Outstanding Service Award at the Design, Automation and Test in Europe 2019 (DATE) in recognition of significant service as DATE 2019 General Chair.

DATE 2019 / © Cruz Garcia

Tobias Schwarzer Awarded at DATE 2019, March 25-29, 2019:

Tobias Schwarzer (Hardware/Software Co-Design, FAU)

Tobias Schwarzer received the PhD Forum Best Poster Prize at DATE 2019 for his poster titled "System-Level Mapping and Synthesis of Data Flow-Oriented Applications on MPSoCs". The prize is supported by EDAA, ACM Sigda and IEEE CEDA.

Tobias Schwarzer receiving the PhD Forum Best Poster Prize at DATE 2019 in Florence. (photographs DATE 2019 / © Cruz Garcia)

Workshop "Scheduling Meets Fixed-Parameter Tractability", Februrary 4-8, 2019:

Prof. Dr. Nicole Megow (UB), Matthias Mnich and Gerhard Woeginger

Prof. Dr. Nicole Megow organised at Lorentz Center Leiden the workshop "Scheduling Meets Fixed-Parameter Tractability".
more information

Emerging Talents Initiative (ETI), January, 2019: Energy-Aware Gearing of System Software for Adaptive Leverage of Renewable Energies

Dr.-Ing. Timo Hönig (Distributed Systems and Operating Systems, FAU)

Dr.-Ing. Timo Hönig received a research grant by the Emerging Talents Initiative (ETI) of FAU for his project "Energy-Aware Gearing of System Software for Adaptive Leverage of Renewable Energies ". The project investigates the effects of the digitisation of power grids on the system-software design for complex computing systems (e.g., operating systems, workload management systems). In particular, usage and utilisation patterns of high-performance computing systems (e.g., HPC clusters) are considered. Following on from this, it is examined how operating patterns are applied by suitable models in control applications for the operation of complex computer systems. This serves to reduce or increase the electrical power demand of systems. Increasing the electrical power demand is necessary in situations where power grids have to be relieved by key consumers due to large quantities of renewable energies within the power grid.
The Emerging Talents Initiative (ETI) is designed to support excellent postdoctoral researchers by providing them with an opportunity to develop scientific independence and establish themselves in their field of research. The programme targets postdoctoral researchers at the beginning of their career whose experience and research profile show potential for a career in research.

Invited Talk, ASECOLab, January 4, 2019: Adaptive Memory Protection for Many-Core Systems

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat gave an invited talk at the University of Hawaii at Manoa (USA).
more information

Events 2018

Member of the National Academy of Science and Engineering (acatech), November, 2018

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU) and
Prof. Dr.-Ing. Ulf Schlichtmann (Chair of Electronic Design Automation, TUM)

Prof. Dr. Jürgen Teich and Prof. Dr.-Ing. Ulf Schlichtmann had been elected as members of Deutsche Akademie der Technikwissenschaften (acatech). The members of the Academy are outstanding scientists and scholars from the fields of engineering and the natural sciences, medicine as well as from the humanities and the social sciences and admitted on the basis of their scientific achievements. About 500 members of acatech currently work together in projects with experts from science and industry. They are also involved in thematic networks of the academy, discussing specific topics of technical sciences and overarching issues with technological political background.
About acatech - National Academy of Science and Engineering
acatech consults independently and comprehensibly, presenting the opportunities and risks inherent to a technological development and showing how the results were obtained and what experts were involved. All working results are published. The principles upon which acatech’s consultation is based are set out in guidelines for political and social consultancy. If complied with, these guidelines ensure that both the political echelons and civil society players will receive science-based, independent, politically neutral advice geared at public welfare.
more information

Day of the Technical Faculty, November 16, 2018
FAU

Dr.-Ing. Timo Hönig, Dr.-Ing. J. Götzfried and Sebastian Maier (FAU)

Dr.-Ing. Timo Hönig, Dr.-Ing. J. Götzfried and Sebastian Maier at the Day of the Technical Faculty.

InvasIC joined the day of the Technical Faculty to present its current research at the FAU. Moreover, Dr.-Ing. Hananeh Aliee won the price for the promotion of young scientists for her dissertation "Reliability Analysis and Optimization of Embedded Systems using Stochastic Logic and Importance Measures".

Dr.-Ing. Hananeh Aliee won the price for the promotion of young scientists.

Best Paper Award, SysTEX'18, Toronto, Canada, October 15, 2018

J. Götzfried and T. Müller (FAU), T. Lazard (University of Rennes 1), G. Santinelli and V. Lefebvre (Tages SAS Solidshield)

The paper "TEEshift: Protecting Code Confidentiality by Selectively Shifting Functions into TEEs" by Titouan Lazard, Johannes Götzfried, Tilo Müller, Gianni Santinelli, and Vincent Lefebvre received the Best Paper Award at this year's Workshop on System Software for Trusted Execution (SysTEX'18). The award was handed over during the workshop which was held on October 15, 2018 in Toronto, Ontario, Canada. The paper presents a tool suite that protects the confidentiality and integrity of code by shifting selected functions into TEEs. The approach works entirely on binary-level and does not require the adaption of source code projects or build environments, nor does it require compiler-level patches.
access the paper

Invited Talk, NTU, August 23, 2018: Mixed Static/Dynamic Application Mapping for NoC-Based MPSoCs with Guarantees on Timing, Reliability and Security

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at Nanyang Technological University (NTU), Singapore.
In this talk, an overview of techniques for systematically mapping parallel program applications to NoC-based multi-core architectures (MPSoCs) was presented. Complex applications requiring heterogenous processing resources are often described by task graphs with data dependencies. Here, nodes present actors or tasks which are typically activated periodically based on the availability of data. One prominent domain of applications fitting this model is stream processing. Here, it is often important to guarantee either bandwidth or execution time requirements. But typically, also security and reliability aspects may exist that impose further constraints on the mapping of the tasks as well as their communication to cores, respectively routes in the underlying NoC.
In the focus of the presentation were techniques called "Hybrid Application Mapping (HAM)". Here, a careful analysis and characterization of symmetric mappings by constellations of cores and routes is explored in a static (compile-time) phase of Design Space Exploration (DSE). At run-time, the operating system then only needs to search within a much smaller space of pre-characterised constellations for finding a concrete mapping that will satisfy the given non-functional constraints by construction.
In order to allow the analysis of applications statically and independently, however, techniques for isolation are needed. This is achieved using a novel programming paradigm called Invasive Computing. Here, cores are "invaded" at run-time for exclusive usage before execution rather than shared. For a rather general class of NoC-based MPSoC architectures, it was shown that HAM allows to provide guarantees not only guarantess on timinig, but also on reliability and on certain security properties on demand of an invididual application through the enforced isolation of resources. As a case study, we applied and demonstrated the concepts for a video-based cyber-physical real-time control application.

Invited Talk, NUS, August 24, 2018: Run-Time Application Mapping in Many-Core Architectures

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at National University of Singapore (NUS).
Many-core architectures enable the concurrent execution of multiple applications within a system. In this context, the well-known problem of feasibly mapping application to resources, i.e., tasks and their communication, has gained attention again due to the large number of cores and limited communication capacities between cores.
Whereas the general graph-based mapping problem is known to be NP-complete, we present a decomposition approach called hybrid mapping (HAM) that characterizes classes of feasible, even optimal mappings wrt. to a set of non-functional properties at compile-time. For the reduced search space run-time mapping problem, two exact approaches for parallel problem solving are then proposed and compared: a backtracking and an approach based on a parallel SAT-solver. For the latter, we presented a novel scheme to partition the architecture and efficiently search in subarchitectures for feasible mappings. Solver instances encoding the complete architecture are only required in the case of the absence of feasible implementations on subarchitectures.
For a class of benchmark applications, the two run-time approaches were analyzed for execution times on different scales of NoC-based many-core targets. Interestingly, the execution times go down for parallel solvers over a single solver instance in both approaches. Also, the backtracking approach can determine solutions within an average of a few milliseconds for large scale architectures even, whereas the parallel SAT-solver techniques suffer from a quite long initialization overhead.

Invited Talk, UTFPR, August 7, 2018: Predictability Issues in Operating Systems

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat gave an invited talk at Technological Federal University of Paraná, Brazil (UTFPR).
Predictability is always subject to the underlying assumptions being made. For real-time systems, time response of processes in relation to the strictness of deadlines is of particular importance. With an additional focus on embedded systems, space and energy requirements become relevant as well and need to be considered in combination. As far as software is concerned, structure and organisation of the programs to be executed determines whether or not predictable processes will take place in a given computing system. Design for predictability is an overarching aspect that crosscuts the whole computing system and particularly addresses operating systems.
This talk is about structuring principles of non-sequential programs - in the shape of but not limited to operating systems - to abet predetermination of quality attributes of non-sequential (real-time) processes, it is not about analytical methods to effectively predetermine these attributes. Issues in operating systems as to space, timing, and energy requirement are touched. Emphasis thereby is on coordination of cooperation and competition between processes, namely synchronisation. It is shown how measures of process synchronisation against the background of many-core processors cater to these issues.

Awarding Habilitation Certificate, FAU, August 2, 2018

Dr.-Ing. habil. Frank Hannig (FAU)

Congratulation to Dr.-Ing. habil. Frank Hannig (FAU) for receiving his habilitation certificate.
Read more about his research activities.

Invited Talk, UNSW, July 31, 2018: Hybrid Application Mapping for NoC-Based MPSoCs with Guarantees on Timing, Reliability and Security

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at the University of New South Wales (UNSW).
In this talk, an overview of techniques for systematically mapping parallel program applications to NoC-based multi-core architectures (MPSoCs) was presented. Complex applications requiring heterogenous processing resources are often described by task graphs with data dependencies. Here, nodes present actors or tasks which are typically activated periodically based on the availability of data. One prominent domain of applications fitting this model is stream processing. Here, it is often important to guarantee either bandwidth or execution time requirements. But typically, also security and reliability aspects may exist that impose further constraints on the mapping of the tasks as well as their communication to cores, respectively routes in the underlying NoC. In the focus of the presentation were techniques called "Hybrid Application Mapping (HAM)". Here, a careful analysis and characterization of symmetric mappings by constellations of cores and routes is explored in a static (compile-time) phase of Design Space Exploration (DSE). At run-time, the operating system then only needs to search within a much smaller space of pre-characterised constellations for finding a concrete mapping that will satisfy the given non-functional constraints by construction. In order to allow the analysis of applications statically and independently, however, techniques for isolation are needed. This is achieved using a novel programming paradigm called Invasive Computing. Here, cores are "invaded" at run-time for exclusive usage before execution rather than shared. For a rather general class of NoC-based MPSoC architectures, it was shown that HAM allows to provide guarantees not only guarantees on timing, but also on reliability and on certain security properties on demand of an individual application through the enforced isolation of resources. As a case study, we applied and demonstrated the concepts for a video-based cyber-physical real-time control application.

Keynote Talk, ISVLSI, Hongkong, July 10, 2018
Power Density and Circuit Aging – System-Level Means for Mitigation

Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT)

Prof. Jörg Henkel at the IEEE Computer Society Annual Symposium on VLSI

Prof. Dr.-Ing. Jörg Henkel gave an invited keynote talk at the IEEE Computer Society Annual Symposium on VLSI in Hong Kong. Power density will stay a major challenge for the foreseeable future. Despite orders-of-magnitude-improved efficiency, power consumption per area is rising, mainly due to the limits of voltage scaling. To investigate the physical implications of high power densities, we must distinguish between peak and average temperatures and temporal and spatial thermal gradients because they trigger circuit-aging mechanisms and eventually jeopardize the reliability of an on-chip system. The talk started by presenting some basic interdependencies in the triangle of power density, circuit aging and reliability and continues with solutions to mitigate the problem via, among others, power density-aware resource management, thermal save power (TSP), efficient power budgeting as well as "Aging Aware Boosting".
more information

Keynote Talk, Adaptive Many-Core Architectures and Systems workshop, York, June 14, 2018
Methodologies for Application Mapping for NoC-Based MPSOCs

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited keynote talk at the Adaptive Many-Core Architectures and Systems workshop in York, UK. In this talk, we gave an overview of novel techniques for systematically mapping applications to NoC-based multi-core architectures (MPSoCs). Complex applications requiring heterogenous processing resources are often described by task graphs with data dependencies. Here, the nodes represent actors or tasks which are typically activated periodically based on the availability of data. One prominent domain of applications fitting this model is stream processing. Here, it is often important to guarantee either bandwidth or execution time requirements. But more recently, also security, energy and reliability aspects impose constraints on the mapping of the tasks as well as their communication to cores, respectively routes in the underlying NoC. Concerning mapping methodologies, we first presented a class of algorithms that perform "Self-Embedding". The idea is here that a source node issues a request to find appropriate resources to embed its sucessor tasks, and so on. The next class of techniques introduced is called "Hybrid Application Mapping (HAM)". Here, a careful analysis and characterization of symmetric mappings by constellations of cores and routes is explored in a static (compile-time) phase called "Design Space Exploration (DSE)". At run-time, the operating system then only needs to search within such pre-analysed constellations for finding a concrete mapping that will satisfy the given non-functional constraints by construction. We present ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that deadlines or throughput requirements will be automatically met for streaming applications. Finally, we conclude with a discussion on resource constellations that may satisfy certain security requirements on an MPSoC.
more information

Invited Talk, Computer Science Colloquium, Hannover, June 29, 2018: Predictability Issues in Operating Systems

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat gave an invited talk at Computer Science Colloquium at Leipniz Universität Hannover.
Predictability is always subject to the underlying assumptions being made. For real-time systems, time response of processes in relation to the strictness of deadlines is of particular importance. With an additional focus on embedded systems, space and energy requirements become relevant as well and need to be considered in combination. As far as software is concerned, structure and organisation of the programs to be executed determines whether or not predictable processes will take place in a given computing system. Design for predictability is an overarching aspect that crosscuts the whole computing system and particularly addresses operating systems.
This talk is about structuring principles of non-sequential programs - in the shape of but not limited to operating systems - to abet predetermination of quality attributes of non-sequential (real-time) processes, it is not about analytical methods to effectively predetermine these attributes. Issues in operating systems as to space, timing, and energy requirement are touched. Emphasis thereby is on coordination of cooperation and competition between processes, namely synchronisation. It is shown how measures of process synchronisation against the background of many-core processors cater to these issues.

Zollhof University Innovation Day, Nürnberg, June 28, 2018:

Mr. Marcel Brand, M.Sc. (Hardware/Software Co-Design, FAU)

The Zollhof University Innovation Day was an event at which students, scientists and companies came together to learn about the innovations that are developed and researched at the Friedrich-Alexander University Erlangen-Nürnberg. In this context Mr. Brand gave a well received talk about the concepts of Invasive Computing and has shown its benefits with an example application, an inverted pendulum application, that combines all concepts into one demonstrator.
more information

Invited Talk, UMass, May 30, 2018: Building a Runtime System for Heterogeneous HPC Clusters to Exploit Dynamic Electricity Pricing

Dr.-Ing. Timo Hönig (Distributed Systems and Operating Systems, FAU)

Dr.-Ing. Timo Hönig gave an invited talk at the College of Information and Computer Sciences, University of Massachusetts Amherst (UMass), USA.
For today's computer systems, electrical energy is the single most important operating resource. The conscious use of energy resources is motivated by different factors and depends on the respective systems and their application: from "smart dust" and battery-powered mobile systems to large-scale high-performance computing clusters that operate under thermal constraints.
Energy awareness is a prerequisite for energy-efficient operations of computers, and effects the program design time (i.e., ahead of run time) and program execution (i.e., at run time) at operating-system level.
This talk presents energy-aware programming techniques that originate in static and dynamic program analyses, and support the design of energy-aware system software. To bridge the gap towards execution time, the talk further discusses Albatross, a runtime system that exploits dynamic electricity prices to ensure cost effectiveness for operating heterogeneous HPC clusters.
more information

DFG grants funding for 3rd research period of Invasive Computing! May 18, 2018

InvasIC

The Collaborative Research Center/Transregio 89 "Invasive Computing" is entering the third approval phase and will be funded for another four years. The German Research Foundation (DFG) is providing 10 million euros for the research of future parallel computing systems. For more information see:
FAU press release in German
DFG press release in German

Invited Talk, HPI, Potsdam, April 20, 2018: Adaptive Memory Protection for Many-Core Systems

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat gave an invited talk at Hasso-Plattner-Institut (HPI) in Potsdam.
Hardware-based memory protection is widely applied in all areas of computing, it is a fundamental building block for safety and security. However, improving protection measures by means of dedicated hardware such as a memory management unit (MMU) is not carved in stone, but rather depends on the application domain and the facts of the programming system and hardware, respectively.
State of the art operating systems statically determine whether or not software entities are subject to memory protection. If enabled, costly operations will follow due to multi-level page-table handling, TLB (translation look-aside buffer) invalidations, and the release of inter-processor interrupts. This all reduces performance, increases operating-system noise, and makes system behavior unpredictable. If application programs are type-safe, then enabled hardware protection becomes a pretty much superfluous features. Contrariwise, if the programs are type-unsafe, disabled hardware protection opens door and gate for malware.
This talk is on adaptive memory-protection that is capable of dynamically changing the per-program protection state. The feature is triggered at load/unload time of application programs and applies in the background of running processes. Measurement results are presented and discussed in terms of timing predictability of the system.

Best Paper Award, DFRWS EU 2018, Florence, March 21-23, 2018
Florence, Italy

Sven Schmitt, Prof. Dr.-Ing. Felix Freiling and Sebastian Nemetz (FAU)

The paper "A Standardized Corpus for SQLite Database Forensics" by Sven Schmitt, Felix Freiling and Sebastian Nemetz received the Best Paper Award at this year's Digital Forensics Research Conference Europe (DFRWS EU 2018). The award was handed over during the conference which was held between March 21-23, 2018 in Florence, Italy. The paper presents a standardized corpus of SQLite files that can be used to evaluate and benchmark analysis methods and tools. The corpus contains databases which use special features of the SQLite file format or contain potential pitfalls to detect errors in forensic programs.
access the paper

Invited Talk, Berkeley, March 16, 2018: Shallow Water on a Deep Technology Stack — Actor-Based Tsunami Simulation using Invasive Computing

Alexander Pöppl (TUM)

Alexander Pöppl (TUM) gave an invited talk at the Lawrence Berkeley National Laboratory in California, USA. Heterogeneous resources such as GPUs, FPGAs and an ever increasing node and core count complicate design and implementation of HPC applications. The traditional bulk synchronous parallelism model and the static approach that applications implementing it follow do not seem to fit these new circumstances. Although the implementation of efficient applications in the aforementioned manner is possible, developers now have to depend on an ever increasing number of frameworks and libraries, for example a combination of MPI for inter-node communication, OpenMP for intra-node communication and CUDA for GPU-specific components. We propose Invasive Computing as an alternative. Invasive applications are implemented in invadeX10, an APGAS language using an actor library, actorX10. Resources are allocated at execution time based on application requirements and the overall system situation. Actors schedule themselves based on information available in their connected channels, which helps to avoid explicit global barriers. Invasive Computing requires support from the entire compute stack. To demonstrate the benefits of our approach, we created a demonstration system encompassing the entire compute stack, including custom hardware, operating system, compiler and applications. For the application layer, we built SWE-X10, an actor-based and locally coordinated tsunami simulation. It uses actorX10 for coordination to implement a time stepping scheme without global barriers. Furthermore, we introduced lazy activation of actors, where actors are gradually enabled once the wave reaches their part of the simulation domain. We also integrated SWE-X10 into the invasive stack. SWE-X10 consistently beats SWE, a prior, MPI+OpenMP-based version in weak scaling tests. Using lazy activation in a radial dam break test scenario, we were able to reduce the computation time (in core hours) by ~40%. Finally, using a custom-built instruction on the invasive platform prototype, we obtained an 3x speed-up for iterations for actors using the custom instruction. One of our goals is to make the actor-based computational paradigm available to a wider audience. Therefore, I plan to implement an actor framework in UPCxx during my stay at Berkeley Lab. As a first use-case, the framework will be integrated with my tsunami application.

Dagstuhl Seminar 18101, March 4-9, 2018: Scheduling

Prof. Dr. Nicole Megow (UB)

Prof. Dr. Nicole Megow organised the Dagstuhl Seminar 18101 on Scheduling jointly with Cliff Stein (Columbia U., US) and Magnus Halldorsson (Reykjavik U., IS). This seminar brought together algorithmically oriented researchers from two communities with interests in resource management: the scheduling community and the networking/distributed computing community. The major goals of the seminar were to expose each community to the important problems and techniques from the other community, and to enable and encourage cooperation among the researchers.
more information

Invited Talk, NII Shonan Meeting, Shonan Village, March 27, 2018: Predictability Issues in Operating Systems

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat gave an invited talk at the NII Shonan Meeting on Resilient Machine-to-Machine Communication in Shonan Village, Japan.
Predictability is always subject to the underlying assumptions being made. For real-time systems, time response of processes in relation to the strictness of deadlines is of particular importance. With an additional focus on embedded systems, space and energy requirements become relevant as well and need to be considered in combination. As far as software is concerned, structure and organisation of the programs to be executed determines whether or not predictable processes will take place in a given computing system. Design for predictability is an overarching aspect that crosscuts the whole computing system and particularly addresses operating systems.
This talk is about structuring principles of non-sequential programs - in the shape of but not limited to operating systems - to abet predetermination of quality attributes of non-sequential (real-time) processes, it is not about analytical methods to effectively predetermine these attributes. Issues in operating systems as to space, timing, and energy requirement are touched. Emphasis thereby is on coordination of cooperation and competition between processes, namely synchronisation. It is shown how measures of process synchronisation against the background of many-core processors cater to these issues.
more information

Invited Talk, LISHA, Florianópolis, February 16, 2018: Predictability Issues in Operating Systems

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat gave an invited talk at the Software/Hardware Integration Lab (LISHA) of the Universidade Federal de Santa Catarina (UFSC), Florianópolis, Brazil.
more information

Panel Discussion, Erlangen, February 9, 2018: Panel Discussion: Digitalisation - Chance or Risk?

Prof. Dr.-Ing. Felix Freiling (FAU)

Prof. Dr.-Ing. Felix Freiling participated in a panel discussion on "Digitalisation - Chance or Risk?" on February 9, 2018 at the Foyercafe of the Markgrafentheater, Erlangen. The discussion captured the positive and negative side effects of digitalisation.

Keynote Talk, VLSID 2018, Pune, January 6, 2018
Power Density and Reliability in Embedded On-Chip Systems

Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT)

Prof. Dr.-Ing. Jörg Henkel gave an invited keynote talk at the 31st International Conference on VLSI Design in Pune, Maharashtra, India. Though power consumption of transistors has steadily decreased, power density is currently the most limiting design factor for many kinds of embedded on-chip systems. Negative side effect of high power densities is a significantly decreased level of reliability. Though this general interdependency is known for long time, a precise quantification of this interdependency did not yet exist. This talk presented the newest findings in circuit aging mechanisms that for the first time allow drawing an accurate design space that comprises all relevant parameters and their interdependencies. Given this design space, guard-bands can be designed more carefully and system-level decisions can better exploit the trade-off between performance, power and circuit lifetime. The talk showed that these findings open new, not-yet-explored optimization potential for embedded on-chip systems.

CAST Förderpreis IT-Sicherheit 2017, Jan. 2018:

Moritz Eckert (FAU)

Moritz Eckert (FAU) ranked first with his bachelor thesis in the CAST Förderpreis IT-Sicherheit 2017. Within his work “Cache-Timing Side-Channel Attacks against Intel's SGX” he implemented the prime practical cache attack against an AES implementation within a secure SGX-enclave. His bachelor thesis was supervised by Johannes Götzfried of the chair Informatik 1within the group System Security and Software Protection.
more information

Events 2017

Fellow of the IEEE, November 20, 2017:

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

The IEEE Board of Directors, at its November 2017 meeting, elevated our coordinator to IEEE Fellow, effective 1 January 2018, with the following citation: "for contributions to hardware/software co-design for embedded systems".

Invited Talk, November 15, 2017: Generating FPGA-based Image Processing Accelerators with Hipacc

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Dr.-Ing. Jürgen Teich gave an invited talk at International Conference on Computer Aided Design (ICCAD 2017), Irvine, USA: Domain-Specific Languages (DSLs) provide a high-level and domainspecific abstraction to concisely describe algorithms within a certain domain. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs became an attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGAs have been proven to be among the most suitable architectures. In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.

Invited Talk, November 14, 2017:
Application Mapping Methodologies for NoC-Based MPSOCs

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Dr.-Ing. Jürgen Teich will give an invited talk at the University of California, Irvine, USA: In this talk, he gave an overview of novel techniques for mapping applications to NoC-based multi-core architectures (MPSoCs). Complex applications requiring hetergenous processing resources are often described by task graphs with data dependencies. Here, the nodes represent actors which are typically executed periodically based on the availability of data. One prominent example of applications is stream processing. Here, it is important to guarantee either bandwidth or execution time requirements, but also security aspects, energy and reliability often impose constraints on the mapping of the tasks as well as the communication to cores, respectively the underlying NoC. Concerning mapping applications, we first present solutions based on self-embedding. The idea is here that a source node issues request to find appropriate resources for the sucessor tasks, and so on. The next class of techniques is called Hybrid Application Mapping (HAM). Here, a careful analysis and characterization of symmetric mappings to constellations of cores and routes is explored in a static phase of design space exploration. At run-time, the operating system then only searches for such constellations to be available for finding a concrete mapping. We present ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that deadlines or throughput requirements will be automatically guaranteed for streaming applications. Finally, we also discuss resource constellations such are able to satisfy certain securit requirements on an MPSoC.

Invasive computing joins the open house event at TUM

Oct. 21, 2017, Garching: Emily Mo-Hellenbrand (TUM) demonstrated invasive computing at the open house event. more information

Outstanding Paper Award and Best Presentation Award

October 6, 2017, Grenoble, France:

Behnaz Pourmohseni, Dr.-Ing. Stefan Wildermann, Prof. Dr.-Ing. Michael Glaß and Prof. Dr.-Ing. Jürgen Teich received the Outstanding Paper Award for their contribution "Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems" at the International Conference on Real-Time Networks and Systems, Grenoble, France. In addition, Behnaz Pourmohseni received the Best Presentation Award. more information

30th IEEE International System-On-Chip Conference (SoCC) 2017

Sep. 7, 2017, Munich: Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT) gave a keynote on "The Triangle of Power Density, Circuit Degradation and Reliability".
Power density will stay a major challenge for the foreseeable future. Despite orders-of-magnitude-improved efficiency, power consumption per area is sharply rising, mainly due to the limits of voltage scaling. To investigate the physical implications of high power densities, we must distinguish between peak and average temperatures and temporal and spatial thermal gradients because they trigger circuit-aging mechanisms and eventually jeopardize the reliability of an on-chip system.
The talk started by presenting some basic interdependencies in the triangle of power density, circuit degradation and reliability and continued with some solutions to mitigate the problem via, among others, power density-aware resource management and efficient power budgeting. more information

30th IEEE International System-On-Chip Conference (SoCC) 2017

Sep. 5-8, 2017, Munich: Prof. Dr.-Ing. Jürgen Becker (KIT) serves as General Chair and Prof. Dr.-Ing. Ulf Schlichtmann (TUM) as Co-Generals Chair of the 30th IEEE International System-On-Chip Conference (SoCC) 2017 in Munich.
more information

Invited Talk, July 21, 2017, at University of Zürich, Switzerland:
Resource Awareness on Heterogeneous MPSoCs for Image Processing

Prof. Dr.-Ing. Walter Stechele (Integrated Systems, TUM)

Multiprocessor System-on-Chip (MPSoC) offers a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding heterogeneous accelerators and specialized hardware with instruction-set extensions. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, especially with respect to predictability in best effort processing. We investigate the benefits of a resource-aware programming model called Invasive Computing for dynamically mapping image processing applications to different types of PEs available on a heterogeneous MPSoC.

GPU Course "Programming and optimizing for heterogeneous CPU-GPU architectures"

May 15-19, 2017, Munich: Prof. Walter Stechele (TUM) organizes the GPU Course "Programming and optimizing for heterogeneous CPU-GPU architectures" at TUM.
The imminent future of parallel architectures is a tighter integration of different types of processing cores, namely CPUs and GPUs. In this course, you will be introduced to the current heterogeneous architectures, and how to program them using mainstream languages, such as CUDA and OpenCL, and higher level languages as C++AMP.
more information

Transfer project "Integration and Coupling of Tightly Coupled Processor Arrays"

April 27, 2017: Dr. Frank Hannig and Prof. Jürgen Teich received a considerable funding from the DFG for their new transfer project (T1), which is part of the CRC/Transregio 89 from now on. In cooperation with their industry partner Infineon Technologies AG they research the topic "Integration and Coupling of Tightly Coupled Processor Arrays".
Objective of this transfer project is the analysis of massively parallel accelerator architectures, in particular tightly coupled processor arrays (TCPAs), and their integration into a commercial state-of-the-art embedded microcontroller architecture such as Infineon’s AURIX, or ARM’s Cortex-A series of processors.
See transfer project for more information.

Invasive Computing at the Hannover Messe

April 24-28, 2017:
At this year's Hannover Messe, Éricles Sousa showcased how Invasive Computing can be used to enforce timing predictability on multi-core systems. Here are some impressions from the fair.

Dr. Santiago Pagani has been awarded the ACM "Paul Caspi Memorial Dissertation Award"

April 19, 2017, Pittsburgh:

Dr. Santiago Pagani (KIT) has been awarded the ACM "Paul Caspi Memorial Dissertation Award" from SIGBED (Special Interest Group Embedded Systems of ACM) for his PhD thesis entitled "Power, Energy, and Thermal Management for Clustered Manycores". The award description reads: "The award recognizes outstanding doctoral dissertations that significantly advance the state of the art in the science of embedded systems, in the spirit and legacy of Dr. Paul Caspi's work". The award includes a certificate for the author and an honorarium of 2000 USD. Dr. Pagani received the award at the recent Cyber-Physical Systems Week (CPSWeek) in Pittsburg that took place from April 18-21, 2017. The photo shows Dr. Pagani at the award ceremony on Wed. April 19th in Pittsburgh.

Joint workshop "InvasIC meets HAEC"

January 17/18, 2017:
SFB 89 "Invasive Computing" and SFB 912 "Highly Adaptive Energy-Efficient Computing" organised a joint workshop in Dresden. Researchers from both SFBs met at Schloss Eckberg. to discuss similarities and differences between the two research groups for two days. As coordinators of the two collaborative research centers Prof. Gerhard Fettweis and Prof. Jürgen Teich, gave an interesting overview when having their opening talks in the first evening. On the second day, researchers from both groups presented ideas and results on the following topics:
- energy efficiency
- power stability
- security
- resilience.
The meeting was very intense with lively discussions and useful dialogues between researchers from InvasIC and HAEC.

Events 2016

it - Information Technology: Thematic Issue on "Invasive Computing"

Dezember, 2016: In the current edition of the journal "it - Information Technology" a Thematic Issue on "Invasive Computing" was published. Four articles were written by members of the CRC/Transregio showing different aspects of our work. Prof. Dustar from TU Wien completed the topic with his article on "Elastic computing".
more information

Third Workshop on Low-Power Dependable Computing (LPDC)

November 2016, Hangzhou, China: Dr. Muhammad Shafique (Karlsruher Institut für Technologie, Germany), Prof. Dr. Xiaomin Zhu (National University of Defense Technology, China) and Prof. Dr. Dakai Zhu (University of Texas at San Antonio, USA) organized the Third Workshop on Low-Power Dependable Computing (LPDC) in conjunction with the 2016 International Green and Sustainable Computing Conference (IGSC) in Hangzhou, China.
more information

Dagstuhl Seminar 16441 "Adaptive Isolation for Predictability and Security"

October 30-November 4, 2016, Dagstuhl: Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU), Prof. Dr.-Ing. Ingrid Verbauwhede (KU Leuven, BE), Prof. Dr.-Ing. Lothar Thiele (ETH Zürich, CH) and Prof. Dr. Tulika Mitra (National University of Singapore, SG) organized and coordinated the Dagstuhl Seminar on "Adaptive Isolation for Predictability and Security".
more information

Appointment to Professorships

Autumn 2016: This year was an outstanding year concerning the professional success of three members of the CRC/Transregio: Prof. Dr.-Ing. Michael Glass (FAU), Dr.-Ing. Muhammad Shafique (KIT) and PD Dr.-Ing. habil. Daniel Lohmann (FAU) were appointed as professors at the highly reputable universities of Ulm, Vienna and Hanover, respectively.

12TH ACM/IEEE Embedded Systems Week (ESWEEK 2016)

Oct. 2-7, 2016, Pittsburgh, USA: Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT) served as General Chair of the ESWEEK 2016.
more information

Invited Talk, July 29, 2016:
Predictability, Fault Tolerance, and Security on Demand using Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at University of Lübeck, Germany:
The talk gives a short introduction and overview of the topic and benefits of invasive multi-core computing for achieving timing predictability, fault tolerance and security for individual application programs. Here, cores, memory regions and network bandwidth are allocated and freed on demand of each user program for obtaining exclusive usage and access.
It will be shown that through the achieved isolation of resources and thus full applications, the variation of execution time may be reduced drastically for many parallel application programs, i.e., soft real-time image and stream processing. This opens also a way for hybrid performance analysis techniques that combine static timing analysis of applications in isolation and run-time assignment of resources for the execution.
Moreover, the isolation is also beneficial for enabling security on a chip as will be shown. Finally, we present an approach to provide on-demand structural redundancy using invasive computing for a class of massively parallel processor arrays called TCPAs. For protecting safety-critical parallel loop program applications against soft errors, known replication schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) must be lifted to many processors (PEs). Depending on application requirements for reliability and observed Soft Error Rates (SERs), different voting options in hardware and software and analysis techniques for automatic replication scheme selection are presented and compared.

The Munich Workshop on Design Technology Coupling

June 30-July 1, 2016, Munich: Dr. Helmut Graeb (TU Munich) and Dr. Sani Nassif (Radyalis) organized in cooperation with the DFG Transregional Collaborative Research Center 89 "Invasive Computing" and the SPP 1500 "Dependable Embedded Systems" the "The Munich Workshop on Design Technology Coupling (DTC)". The workshop involved different contributions from industry, e.g., Infineon AG, Bosch GmbH, and Volkswagen AG, as well as from the two DFG-funded research programs. In one session, Prof. Teich gave a short introduction and overview of the topic and benefits of invasive multi-core computing for achieving timing predictability, fault tolerance and security for individual application programs. This talk was followed by the following overviews on providing fault tolerance and power management through invasive computing, "Providing Fault Tolerance Through Invasive Computing" by Dr. Vahid Lari (FAU) and "On-Chip Diagnosis of Multicore Platforms for Power Management" by Mark Sagi (TUM). Furthermore, on 1st of July, the following demonstrations have been presented: An invasive object tracking application that was simulated and visualized in real-time using C2's simulator InvadeSIM, and the code generation for Safe(r) loop computations using the C3's compilation flows.
more information

Special Session at Design Automation Conference (DAC 2016)

June 8, 2016, San Francisco, USA: Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT) and Dr.-Ing. Muhammad Shafique (KIT) organised a Special Session on "Cross-Layer Approximate Computing: Challenges and Solutions" at the DAC 2016. more information

Invited Talk, June 6, 2016:
Predictable MPSoC Stream Processing Using Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at University of Texas at Austin, USA:
Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds. Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource (e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time. This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems.
Static solutions to provide the required isolation by allocating distinct resources to safety- or performance-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.
In this talk, we first review and present novel definitions of predictability of execution qualities. Subsequently, we distinguish two techniques for improving predictability called restriction and isolation and present new definitions. Then, new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC are introduced based on the paradigm of Invasive Computing. In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In Invasive Computing, isolation is supported on all levels of hardware and software including the OS. Together with restriction (of input uncertainties), the level of on-demand predictability of program execution qualities may be fundamentally increased.
For a broad class of streaming applications, and a concrete demonstration based on a complex object detection application algorithm chain taken from robot vision, we show how jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications.

29th GI/ITG International Conference on Architecture of Computing Systems (ARCS)

April 4-7, 2016, Nuremberg: The 29th International Conference on Architecture of Computing Systems (ARCS 2016) was hosted by the Department of Computer Science at Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany, during April 4–7, 2016. ARCS 2016 took place in Nuremberg at FAU’s Faculty of Business, Economics, and Law in Nuremberg and attracted 100 participants. The conference continued the long-standing ARCS tradition of reporting top-notch results in computer architecture and other related areas. ARCS was founded in 1970 by the German computer pioneer Prof. Wolfgang Händler, who also founded the Computer Science Department at FAU in 1966.
In the welcome address, General Chair Dietmar Fey and Program Chair Frank Hannig, both FAU, highlighted the privilege of having brought ARCS back to its roots in honor of the CS Department’s 50th anniversary and provided statistics on the submissions. In response to the call for papers, 87 submissions were received with affiliations to 31 countries, which clearly demonstrates ARCS’s international character, although a large share (39%) was coming from authors in Germany. With the help of 61 members of the Technical Program Committee, who carried out 325 reviews (about four per submission) and having intensely scrutinized the reviews, we were pleased to present a high-quality technical program that included a total of 29 papers (33%) at the conference.
The strong technical program was complemented by three keynote talks on: "Knights Landing Intel Xeon Phi CPU: Path to Parallelism with General Purpose Programming" by Avinash Sodani, Chief Architect ’Knights Landing’ Xeon-Phi processor at Intel Corporation; "Massive Parallelism – C++ and OpenMP Parallel Programming Models of Today and Tomorrow" by Michael Wong, CEO of OpenMP Corporation; and "Heterogeneous Systems Era" by John Glossner, President of the Heterogeneous System Architecture Foundation (HSAF) and CEO Optimum Semiconductor Technologies; as well as five workshops and a tutorial.
Beside the technical program, the combined visit of the special exhibition "From Abacus to Exascale – Vom Abakus zu Exascale", the conference dinner and best paper award ceremony in the Museum of Industrial Culture in Nuremberg on Wednesday evening was another highlight.

John Glossner and Zoran Salcic visited the TCRC

In the context of ARCS 2016, Dr. John Glossner, President of the Heterogeneous System Architecture Foundation (HSAF) and CEO of Optimum Semiconductor Technologies, and Prof. Zoran Salcic, The University of Auckland, New Zealand, visited also the Transregional Collaborative Research Center Invasive Computing.

InvasIC at Hannover Messe 2016

April 25-29, 2016 Hannover, Germany: This year´s Hannover Messe attracted over 190.000 visitors intent on future-proofing their operations and investing in state-of-the-art-technology. At the Research & Technology area Sascha Roloff presented a demonstrator showing the principles of Invasiv Computing.

International Workshop on Multi-Objective Many-Core Design (MOMAC)

April 4/5, 2016, Nuremberg, Germany: Michael Glass and Stefan Wildermann (FAU) organized the Third International Workshop on Multi-Objective Many-Core Design (MOMAC) at the ARCS 2016 at FAU’s Faculty of Business, Economics, and Law in Nuremberg. Dr. Felix Reimann (Audi Electronics Venture GmbH, Gaimersheim, Deutschland) gave a keynote talk on "Towards A Holistic Design Space Exploration for Automotive E/E Architectures".
more information

First Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing

March 18, 2016, Dresden, Germany: Walter Stechele (TUM), Cristina Silvano (Politecnico di Milano) and Stephan Wong (TU Delft) organized the "First Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing". This Friday-Workshop related to Invasive Computing was collocated at DATE 2016 in Dresden.
more information

Invited Talk, March 18, 2016:
Adaptive Restriction and Isolation for Predictable MPSoC Stream Processing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited keynote talk at First Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing, DATE 2016 in Dresden, Germany:
Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds. Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource (e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time. This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems.
Static solutions to provide the required isolation by allocating distinct resources to safety- or performance-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.
In this invited talk, we first review and present novel definitions of predictability of execution qualities. Subsequently, we distinguish two techniques for improving predictability called restriction and isolation and present new definitions. Then, new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC are introduced based on the paradigm of Invasive Computing. In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In invasive computing, isolation is supported on all levels of hardware and software including the OS. Together with restriction (of input uncertainties), the level of on-demand predictability of program execution qualities may be fundamentally increased.
For a broad class of streaming applications, and a concrete demonstration based on a complex object detection application algorithm chain taken from robot vision, we show how jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications.

Design, Automation and Test in Europe (DATE) 2016

March 14-18, 2016, Dresden: DATE combines the world’s favorite electronic systems design and test conference with an international exhibition for electronic design, automation and test, from system-level hardware and software implementation right down to integrated circuit design. The DATE conference was held at the International Congress Centre Dresden, Germany, from March 14 to 18, 2016.
Out of a total of 829 paper submissions received, a large share (42%) was coming from authors in Europe, 29% of submissions are from Asia, 25% from North America, and 4% from the rest of the world. This clearly demonstrates DATE’s international character, its global reach and impact.
For the 19th successive year, DATE has prepared an exciting technical programme, says Jürgen Teich, Programme Chair of DATE 2016. With the help of 327 members of the Technical Program Committee, who carried out more than 3000 reviews (about four per submission), finally 199 papers (24%) were selected for regular presentation and 81 additional ones (10%) for interactive presentation.
The conference started on Monday with 10 in-depth technical tutorials offered from experts of the industrial and academic worlds on innovative as well as foundational topics related to design solutions, power efficiency, the internet of things, secure systems and testing and diagnosis. In the evening, the well-established PhD Forum allowed selected PhD students from many nationalities to present their PhD thesis work.
As part of the opening ceremony on Tuesday chaired by General Chair Luca Fanucci, University of Pisa and Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, plenary keynote speakers were Luc Van den hove, President and Chief Executive Officer imec talking on “From the happy few to the happy many: towards an intuitive internet of things.”, and Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys talking about “Design will make everything different”. On the same day, the Executive Track offered a series of business panels discussing hot topics. Executive speakers from companies leading the design and automation industry addressed some of the complexity issues in electronics design and discuss about the advanced technology challenge.
The main conference programme from Tuesday to Thursday included 77 technical sessions organized in parallel tracks from the four areas
D – Design Methods and Tools
A – Application Design
T – Test and Robustness
E – Embedded Systems Software
and several special sessions on Hot Topics such as 3D ICs, In-Memory Computing, Heterogeneous Computing, New Transistor for Hardware Security, Embedded Tutorials on Analog-/Mixed Signal Verification Methods and on the Dark Silicon Problem as well as two sessions on selected EU Projects. In addition, the exciting programme of DATE 2016 included a panel on past and future challenges in EDA.

The conference was complemented by an exhibition which ran for three days (Tuesday – Thursday), offering a comprehensive overview of commercial design and verification tools including vendor seminars and abundant networking possibilities with fringe meetings. This year, there were dedicated campus booths with focus on major trends shaping the future of microelectronics such as IoT and secure systems, Ultra-Low power technologies (FDSOI), 5G wireless networks, 3D-IC integration and automotive systems. Finally, the conference closed on Friday with 8 attractive Friday workshops.

more information

Invited Talk, February 26, 2016:
RaPping and Compilation for Highly Dynamic Parallelism

Prof. Dr.-Ing. Gregor Snelting (IPD, KIT)

Prof. Snelting gave an invited talk at University Saarbrücken, Germany.
PDF

Dagstuhl Seminar 16052 "Dark Silicon: From Embedded to HPC Systems"

January 31-February 3, 2016, Dagstuhl: Prof. Dr. Gerndt (TUM), Sri Parameswaran (UNSW – Sydney, AU), Barry L. Rountree (LLNL – Livermore, US) and Prof. Dr.-Ing. Glaß (FAU) organizied and coordinated the Dagstuhl Seminar 16052 on "Dark Silicon: From Embedded to HPC Systems":
The goal of this Dagstuhl Seminar is to bring together experts from the different domains and to discuss the state-of-the-art and identify future collaboration topics based on common research interests. We will have three main parts on the topics Dark Silicon, Power and Energy Usage in HPC, and Hybrid Approaches to Resource Management with longer overview presentations by invited speakers and research presentations by the attendees. Each part will close with a discussion slot. After these three parts we plan for group discussion to identify future collaborative research directions.
more information

Invited Keynote Talk, January 19, 2016:
Symbolic Loop Parallelization for Adaptive Multi-Core Systems - Recent Advances and Benefits

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited keynote talk at IMPACT 2016 in Prague, Czech Republic:
With the advent of heterogeneous many-core systems including GPUs and coupled with CPUs and coarse-grain accelerator processor arrays, massively parallel computing on-a-chip is becoming more and more attractive, even for multiple concurrent parallel applications competing dynamically for a certain number and type of processor and memory resources. In this realm, current research initiatives such as Invasive Computing investigate novel solutions how to allocate available resources dynamically between competing applications upon their request to to obtain smallest execution times and achieve high resource utilizations.
In this context, nested loop programs not only form an important source of workload also for the above class of emerging many-core platforms due to their regular computations in polyhedral domains of iterations, but still impose a number of difficult problems to solve in order to adapt a schedule and mapping of a loop nest adaptively to an available region of processors which is not known in size and location until run-time.
In this keynote, symbolic (parametric) loop parallelization techniques are proposed as a remedy to avoid any time- or memory-intensive in-situ compilation on a chip at run-time. Here, some recent results will be summarized how an important class of nested loop programs with parameterized loop bounds may be scheduled and assigned optimally to virtual regions of processors without any need of recompilation at run-time by producing parameterized assembly programs and a proper run-time schedule candidate selection code that initializes the processor codes.
These results may be applied to a multitude of loop nests stemming from numerical benchmarks to signal processing applications to provide predictable and low cost solutions with adaptive speed and ultra-low power consumption. The presented symbolic loop parallelization techniques is applied to a class of massive parallel processor arrays called tightly coupled processor arrays (TCPAs) which allow for non-atomic inter-processor data transfers which are scheduled together with the loop statements. Finally, it is shown that symbolic loop transformations in the polyhedral model not only enable predictable execution time processing for loop nests, but also enable to specify fault-tolerance aspects adaptively. more information

Invited Keynote Talk, January 18, 2016:
The Role of Restriction and Isolation for Increasing the Predictability of MPSoC Stream Processing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited keynote talk at RAPIDO 2016 in Prague, Czech Republic:
Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds.Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource (e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time.This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems.
Static solutions to provide the required isolation by allocating distinct resources to safety-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.
In this keynote, we first review definitions of predictability. We distinguish two techniques for improving predictability called restriction and isolation and present new definitions for predictability. Subsequently, new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC are introduced based on the paradigm of Invasive Computing. In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In invasive computing, isolation is supported on all levels of hardware and software including an invasive OS. Together with restriction (of input uncertainty), the level of on-demand predictability of program execution qualities may be fundamentally increased.
For a broad class of streaming applications, and a particular demonstration based on a complex object detection application algorithm chain taken from robot vision, we show how jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications. more information

Events 2015

Special Session at International Conference on Computer-Aided Design (ICCAD 2015)

November 2, 2015, San Jose, USA: Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT) organised a Special Session on "Dennard Scaling is History and Moore's Law is Aging: How to break the Inevitable Power Wall??" at the ICCAD 2015. more information

Invasive Computing at the "Lange Nacht der Wissenschaften"

October 24, 2015, Erlangen: Researchers and students of Project C2 vividly demonstrated the principles of Invasive Computing at the Long Night of Sciences ("Lange Nacht der Wissenschaften") in Erlangen. For this purpose, a pan-tilt-zoom camera in form of a Martian was tracking a tennis ball, which could be freely moved by the visitors in the entire room. This object tracking application was simulated and visualized in real-time using C2's simulator InvadeSIM. Hereby, the visitors got fundamental insights into tomorrow's multi-core processor architectures and the concepts of Invasive Computing. more information

DATE 2016 TPC Meeting in Nuremberg, October 29, 2015

Programme Chair Prof. Teich hosted the Design Automation and Test in Europe (DATE 2016) TPC Meeting in the Nürnberger Akademie, Nuremberg. More than 200 participants from all over the world attented this meeting to select the technical programme for DATE 2016 that will take place in March 14-18, 2016 in Dresden. Out of a total of 829 paper submissions received, a large share (42%) is coming from authors in Europe, 29% of submissions are from Asia, 25% from North America, and 4% from the rest of the world. This clearly demonstrates DATE’s international character, its global reach and impact. For the 19th successive year DATE has prepared an exciting technical program. With the help of 327 members of the Technical Program Committee who carried out 3062 reviews (about four per submission), finally 199 papers (24%) were selected for regular presentation and 81 additional ones (10%) for interactive presentation.

Special Session at 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2015)

September 30, 2015, Vancouver, Canada: Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT) and Dr.-Ing. Muhammad Shafique (KIT) organised a Special Session on "Dark Silicon – From Computation to Communication?" at the NOCS 2015. more information

Invited Keynote Talk, September 24, 2015:
Resource Awareness on Heterogeneous MPSoCs for Image Processing

Prof. Dr.-Ing. Walter Stechele (Integrated Systems, TUM)

Prof. Stechele gave the keynote talk "Resource Awareness on Heterogeneous MPSoCs for Image Processing" at DASIP 2015 in Cracow, Poland.
Multiprocessor System-on-Chip (MPSoC) offers a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, especially with respect to predictability in best effort processing. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to underutilization of some type of PEs while overloading others.
We investigate the benefits of a resource-aware programming model called Invasive Computing for dynamically mapping image processing applications to different types of PEs available on a heterogeneous MPSoC. Results from visual object recognition tasks indicate that resource-aware programming helps to improve the throughput and worst observed latency of the application program along with better overall workload distribution within the heterogeneous MPSoC.
more information

Siemens Masterpreis 2015

July 30, 2015: Michael Schadhauser (Hardware/Software Co-Design, FAU) received the Siemens Masterpreis 2015 (Siemens Corporate Technology) for his master's thesis "Wissensmanagement in Cyber-Physical Systems mit Techniken des Semantic Web". more information

Special Session at 52nd ACM/EDA/IEEE Design Automation Conference (DAC 2015)

June 11, 2015, San Francisco, USA: Dr.-Ing. Muhammad Shafique (KIT) organised a Special Session on "Dark Silicon: No Way out?" at the DAC 2015. more information

DAC 2015

June 7-11, 2015, San Francisco: Sascha Roloff gave a talk about "Execution-Driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures", which was accepted as full paper at the Design Automation Conference (DAC) 2015 in San Francisco. Furthermore, he and the masters student David Schafhauser presented a poster about this paper at the DAC exhibiton area.

ACM SIGDA Outstanding New Faculty Award

June 7-11, 2015, San Francisco: Dr.-Ing. Muhammad Shafique, Research Group Leader at Karlsruhe Institute of Technology (KIT), received the 2015 ACM SIGDA Outstanding New Faculty Award for demonstrating an outstanding potential as a lead researcher and/or educator in the field of electronic design automation.

Invited Talk, June 7, 2015, San Francisco, USA:

Dr.-Ing. Muhammad Shafique (Chair for Embedded Systems, KIT)

Dr.-Ing. Muhammad Shafique gave an invited talk at the Workshop on System-to-Silicon Performance Modeling and Analysis which was part of the 52st ACM/EDA/IEEE Design Automation Conference (DAC 2015). He talked about "Application-Driven Power Management for On-Chip Memories". more information

Invited Keynote Talk, June 02, 2015:
Adaptive Isolation for Predictable MPSoC Stream Processing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave the keynote talk "Adaptive Isolation for Predictable MPSoC Stream Processing" at Scopes 2015 in St. Goar, Germany.
Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds. Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource (e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time. This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems. Static solutions to provide the required isolation by allocating distinct resources to safety-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.
In this keynote, we propose new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC based on the paradigm of Invasive Computing. In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In invasive computing, isolation is supported on all levels of hardware and software including an invasive OS. In case of an abundant number of cores available on an MPSoC today, the problem still becomes how to find suitable claims that will guarantee a performance bound and how to find these, if existing, in a negligible amount of time? For a broad class of streaming applications, we propose a combined static/dynamic approach based on a static design space exploration phase to extract a set of satisfying claim characteristics. For a classe of compositional, but not necessarily homogeneous MPSoC systems, only very little information must then be passed to the OS for run-time claim search in the form of so-called CCGs (claim constraint graphs). We demonstrate the above concepts for a complex object detection application algorithm chain taken from robot vision to show jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications.
more information

Faszination Technik: "Wieviele Prozessoren passen in eine Hosentasche?"

April 30, 2015, Erlangen: Dr.-Ing. Stefan Wildermann (Hardware/Software Co-Design, FAU) will give a talk on "Wieviele Prozessoren passen in eine Hosentasche?". This event is part of a series of lectures at the Fraunhofer Institut für Integrierte Schaltungen IIS in Erlangen. more information
Abstract: Heutige Chips enthalten nicht einen sondern mehrere Rechenkerne. Anwendungen im Bereich der Signal-, Audio- und Videoverarbeitung profitieren von der hohen Parallelität, wodurch immer mehr „smarte“ Gerätschaften Einzug in unseren Alltag finden. Um die Rechenleistung weiter zu steigern, werden Mikroprozessoren in naher Zukunft sogar hunderte Kerne beinhalten. Doch bereits jetzt befinden sich Milliarden Transistoren auf einem einzigen Chip, die gar nicht gleichzeitig arbeiten können, weil er sonst zu heiß würde. Hier kann nur durch neuartige Techniken ein Zuwachs der Rechenleistung erreicht werden. Daneben müssen Anwendungen sinnvoll programmiert und im Betrieb verwaltet werden, um die verfügbare Parallelität zu nutzen, und auch sicherheitskritische Systeme im Automobil und der Luftfahrt realisieren zu können. Dieser Vortrag stellt aktuelle Trends und Forschungsarbeiten in diesem Themengebiet vor.

International Workshop on Multi-Objective Many-Core Design (MOMAC)

March 24, 2015, Porto, Portugal: Stefan Wildermann and Michael Glass (FAU) organized the Second International Workshop on Multi-Objective Many-Core Design (MOMAC) at the ARCS 2015.
more information

Keynote Talk, March 24, 2015:
Run-Time Resource and Reliability Management in Dark Silicon Many-Core Chips

Dr.-Ing. Muhammad Shafique (Chair for Embedded Systems, KIT)

Dr. Shafique gave the keynote talk "Run-Time Resource and Reliability Management in Dark Silicon Many-Core Chips" at the Second International Workshop on Multi-Objective Many-Core Design (MOMAC) at the ARCS 2015 in Porto, Portugal.
Due to the technology scaling in the nano-era, the discontinuation of Denard's scaling results in sharp increase in power densities in many-cores that cannot be compensated with cost-efficient cooling mechanisms. Consequently, it leads to the dark silicon problem, where a significant amount of on-chip components in a many-core system cannot be simultaneously powered-on for a given thermal design power (TDP) constraint and stay dark (i.e. power-gated) or at least will be prohibited to operate simultaneously at full speed. Moreover, these high power densities result in high on-chip temperatures that worsen reliability of the many-core systems. The emergence of dark silicon introduces new challenges and opportunities for design and management of many-cores so as to improve quality metrics (performance, reliability, etc.) within peak power and thermal constraints. This talk will provide a short introduction to power-density, temperature, and reliability problems followed by a brief survey of the early explorations on addressing the dark silicon problem. Afterwards, this talk will present novel techniques for efficient resource and reliability management to improve performance and reliability of many-cores under peak power and thermal constraints. more information

Talk, March 18, 2015, New Dehli, India:

Dr.-Ing. Muhammad Shafique (Chair for Embedded Systems, KIT)

Dr.-Ing. Muhammad Shafique gave a talk at the Memory Architecture and Organisation Workshop 2014 which was part of the ESWEEK 2014/ Workshop at CODES+ISSS. He talked about "Application-Driven Power Management for On-Chip Memories". more information

Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) co-located with DATE 2015

March 13, 2015, Grenoble, France: Frank Hannig, Dietmar Fey (FAU, Germany) and Anton Lokhmotov (ARM, Cambridge, UK) organised the Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) at the DATE 2015. more information

Workshop: InvasIC meets AVACS, February 11, 2015

This workshop on Predictability and Dependability took place at Parkhotel Schmid in Adelsried.
meeting place

IEEE Fellow

January 1, 2015 (effective), Atlanta, USA: Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT) was appointed IEEE Fellow because of his contributions to hardware/software codesign of embedded computing systems. The award ceremony took place in June 2015.
more information

Events 2014

Keynote Talk, October 21, 2014:
Dependability of On-Chip Systems in the Dark Silicon Era

Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT)

Prof. Dr.-Ing. Jörg Henkel gave the keynote talk "Dependability of On-Chip Systems in the Dark Silicon Era" at the 32nd IEEE International Conference on Computer Design (ICCD) 2014 in Seoul.
Dependability has become a major design concern as device scaling approaches its limits. Smaller feature sizes lead to higher susceptibility to soft errors, higher process variability and to an accelerated aging of devices. The latter is directly related to temperature, which in fact is responsible for various causes of aging effects like electro migration, NBTI etc. And high on-chip temperature, through high power densities, will enforce to keep some on-chip components idle or at least to prohibit operating them simultaneously at full speed. That is also called “Dark Silicon”. The talk starts by giving an introduction to various reliability jeopardizing effects like aging, the impact temperature has on these and the discontinuation of Dennard Scaling. After presenting the newest research results on the inter-relationship between aging effects, the talk focuses on various techniques to enhance dependability of on-chip systems in the upcoming dark silicon era. more information

Invited Talk, October 16, 2014, New Delhi, India:

Prof. Jürgen Teich (FAU)

Prof. Jürgen Teich gave an invited talk at Multikonferenz Software Engineering & Management 2015 in Dresden. He talked about "Invasives Rechnen" at the special track "Software Engineering in der DFG". more information

Keynote Talk, October 8, 2014:
Invasive Computing - Principles and Benefits

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave the keynote talk "Invasive Computing - Principles and Benefits" at DASIP 2014 in Madrid.
Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present as a new paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs.
The main goal of invasive computing is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects. Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources. The result of an invasion phase is a so-called claim of resources. After termination of a computationally demanding execution phase, the application may release the resources again back to the pool in a phase called retreat. Through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties shall become possible as well.
In the talk, we provide results of the DFG-funded collaborative reseach center TR89 on invasive computing including a) a language definition and implementation for invasive computing based on X10 as developed by IBM. Moreover, we will show how invasive programs may be b) efficiently simulated so to have a testbed for invasive application developers, resource-aware programming, and design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization. Finally, c) a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of video processing algorithm to be executed as a QoS tradeoff with image quality. more information

Invited Talk, September 25, 2014:
System-Level Design Automation of Embedded Systems

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave a talk about "System-Level Design Automation of Embedded Systems" at the meeting of Deutsche Forschungsgesellschaft für Automatisierung und Mikroelektronik e.V. (DFAM). DFAM

Special Session at CODES+ISSS'14, Embedded Systems Week

October 13, 2014, New Delhi, India: Dr.-Ing. Muhammad Shafique (KIT) and Prof. Siddharth Garg (University of Waterloo, Canada) organised a Special Session at CODES+ISSS on "Dark Silicon as a Challenge for Hardware-Software Co-Design". CODES+ISSS 2014 was part of the Embedded Systems Week 2014.
more information

Best Paper Award at CODES+ISSS 2014

October 15, 2014: Santiago Pagani, Heba Khdr, Waqaas Munawar, Jian-Jia Chen, Muhammad Shafique, Minming Li, and Prof. Dr.-Ing. Jörg Henkel received the Best Paper Award for their contribution "TSP: Thermal Safe Power - Efficient power budgeting for Many-Core Systems in Dark Silicon" in the IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Delhi, India, October 2014. more information

DAAD Winter School Tunis, November 26, 2014, Invited Lecture
Coarse-Grained Reconfigurable Architectures - Design and Programming

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich was invited to give a lecture about "Coarse-Grained Reconfigurable Architectures - Design and Programming" in Tunis, Tunesia. The lecture was part of a winter school on "Design, Programming and Applications of Multi-Processor Systems on Chip". more information

Special Session on "Resource-aware and Domain-specific Computing" at ASILOMAR'14

November 3, 2014, Pacific Grove, USA: Dr.-Ing. Frank Hannig (FAU) organised the Special Session on "Resource-aware and Domain-specific Computing" at the Asilomar Conference on Signals, Systems, and Computers.
more information

Workshop on "A Roadmap for EDA Research in the Dark Silicon Era" (ICCAD'14)

November 6, 2014, San Jose, USA: Dr.-Ing. Muhammad Shafique (KIT) and Prof. Siddharth Garg (University of Waterloo, Canada) organised a workshop on "A Roadmap for EDA Research in the Dark Silicon Era" as a collocated event at the International Conference on Computer-Aided Design (ICCAD).
This workshop was intended to provide a common platform for EDA experts to discuss their vision and perspectives on the dark silicon problem, and to define a research roadmap for the next decade. This workshop brought together researchers and experts from industry and academia to dwell on whether fundamentally new solutions are required in the context of dark silicon, or conversely, whether existing solutions can be retro-fitted to address these problems. In either scenario, a lively, but informative technical debate is envisioned that will help to carve out a distinct niche for dark silicon research. In keeping with its intent to encourage a diversity of opinions, this workshop will attempt to include speakers in the agenda with alternate perspectives (“dark silicon is just old wine in a new bottle!”).
more information

24th International Conference on Field Programmable Logic and Applications (FPL 2014)

Prof. Dr. Andreas Herkersdorf (TUM)

September 2-4, 2014, Munich, Germany: The International Conference on Field Programmable Logic and Applications (FPL), organised by Prof. Dr. Andreas Herkersdorf (TUM) is the first and largest conference covering the rapidly growing area of field-programmable logic. During the past 23 years, many of the advances achieved in reconfigurable system architectures, applications, embedded processors, design automation methods (EDA) and tools have been first published in the proceedings of the FPL conference series. Its objective is to bring together researchers and practitioners from both academia and industry from all over the world.

SBBCI 2014 Test of Time Award

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

September 2014, Brasil: Prof. Teich wins the Test of Time Award 2014 of the conference SBCCI (Symposium on Integrated Circuits and Systems Design) for his contribution "Task Scheduling for Heterogeneous Reconfigurable Computers" published in SBCCI 2004. The Test of Time Award 2014 was given to the most cited papers of the SBCCI 2004 edition.

Seminar, July 29, 2014, Montreal:
Foundations and Benefits of Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave a seminar about "Foundations and Benefits of Invasive Computing" at McGill University in Montreal.
McGill University

Invited Talk, June 23, 2014, D.E. Shaw Research, New York:
Automatic Tailoring of System Software: Rethinking the Application–Hardware Bridge

Dr.-Ing. Daniel Lohmann (Computer Science IV, FAU)

System software provides no business value of its own. Its sole purpose is to provide the “right” set of abstractions for the particular application use case: The functional and nonfunctional requirements of the application have to be mapped efficiently to the functional and nonfunctional properties of the hardware. The “ideal” system software does not impair the resulting footprint, robustness, scalability, or predictability by abstractions and policies that do not serve the application’s needs. Between the application and the hardware, the effects of system software should be as “thin” as possible.
In our research, we address this goal by the automatic application--hardware specific tailoring of system software. Platform-specific hardware particularities are not blindly abstracted, but embraced and exploited to offload system services to hardware wherever possible. Our targets reach from automotive hard real-time systems on standard hardware (Sloth) over Linux-based special-purpose systems (VAMOS) to future parallel computing systems based on customized hardware and compiler technology (Invasive Computing). The resulting systems excel with respect to many important nonfunctional properties, including memory footprint, event latency, priority obedience, jitter, and throughput.
» more information Sloth
» more information VAMOS

International Conference on Supercomputing (ICS'14)

June 10-13, 2014 Munich, Germany: Prof. Michael Gerndt (TUM) is co-organiser of the "International Conference on Supercomputing", the premier international forum for the presentation of research results in high-performance computing systems.
more information

Special Session at 51st ACM/EDA/IEEE Design Automation Conference (DAC 2014)

June 3, 2014, San Francisco, USA: Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT) organised a Special Session on "Embedded Resiliency: Approaches for the next Decade" at DAC 2014. more information

DAC 2014 Designer Track Best Poster Award

June 1-5, 2014, San Francisco, USA: Poster "Application-Specific Hierarchical Power Management for Multicast High Efficiency Video Coding", by Muhammad Usman Karim Khan, Muhammad Shafique and Prof. Dr.-Ing. Jörg Henkel, at Designer Track, 51st ACM/EDA/IEEE Design Automation Conference (DAC 2014), San Francisco, CA, USA, June 1-5, 2014.
more information

DAC 2014 Perspective Paper on Dark Silicon

June 1-5, 2014, San Francisco, USA: Titled, "The EDA Challenges in the Dark Silicon Era", on Temperature, Reliability and Variability Perspectives, by Muhammad Shafique, Siddharth Garg, Diana Marculescu and Prof. Dr.-Ing. Jörg Henkel, 51st ACM/EDA/IEEE Design Automation Conference (DAC 2014), San Francisco, CA, USA, June 1-5, 2014.

Workshop on Resource awareness and adaptivity in multi-core computing (Racing 2014)

May 29-30, 2014, Paderborn, Germany: Prof. Dr.-Ing. J. Teich (FAU) and Dr. Frank Hannig (FAU) organised the first Workshop on Resource awareness and adaptivity in multi-core computing (Racing 2014) at the IEEE European Test Symposium (ETS). The steady advances in semiconductor technology allow for increasingly complex SoCs, including multiple (heterogeneous) micro processors, dedicated accelerators, large on-chip memories, sophisticated interconnection networks, and peripherals. However, design, verification, and test as well as parallel programming of such complex multi-core architectures are very challenging since they may have to deal with highly dynamic workloads in different application scenarios and environments. In addition, the architecture might alter itself, either intentionally (e.g., dynamic voltage/frequency scaling, power management) or unintentionally (e.g., failures, aging). As a remedy, one recent research trend in multi-core computing is to design control loops across all platform layers, from application and run-time software down to the status of the underlying hardware. Concepts such as resource-aware programming and adaptive computing are promising candidates for optimizing multi-core systems at run-time with respect to several objectives (utilization, performance, temperature, energy, reliability, dependability, etc.). On the other hand, the enhanced flexibility and adaptivity of such systems raises questions on the predictability of program execution.
The Racing Workshop aims at bringing together researchers and experts from both academia and industry to discuss and exchange research advances from different disciplines in design and test of multi-core architectures as well as programming and run-time management. A distinctive feature of the workshop is its cross section through the entire software/hardware stack, ranging from programming down to multi-core hardware. Thus, Racing is targeted for all of those who are interested in understanding the big picture and the potential of resource-aware and adaptive multi-core computing, its challenges, available solutions, and enables for collaboration of the different domains.
more information

Invited Talk, May 23, 2014, University of Bologna, Italy:
Foundations and Benefits of Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an Invited Talk in the Seminar Series "Trends in Electronics" at the University of Bologna.

InvasIC is being funded for another term of 4 years!

May 16, 2014: The Grants Committee of the DFG approved the extension of CRC/Transregio 89 for an additional funding period.
short note from May 20, 2014,
press report

Session at HiPEAC Computer Systems Week 2014, Barcelona, Spain:
Dynamic co-optimization of applications and resource management

Keynote Talk, May 13, 2014:
The Dark Silicon Problem in Multi-Core Systems - Invasive Computing as a Solution
Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT)

Barcelona, Spain, May 2014: As multi-core systems grow more and more complex and at the same time applications’ behavior is less predictable, the so called Dark Silicon problem becomes a severe issue: since Dennard Scaling cannot be sustained any longer, the power density of on-chip multi-core systems reaches levels where not all cores can run at full speed at the same time.
Hence, some cores need to stay “dark” in order meet the thermal design power constraint. Since “dark” cores represent an inefficient way of operating a multi-core system and even question further scaling, sophisticated means for resource management are demanded.
The talk gives an introduction to Invasive Computing, a highly adaptive resource-aware computing paradigm. It is shown that adaptive resource management can indeed alleviate the Dark Silicon problem, allowing operating more cores at a higher speed as to what the thermal design power constraint would allow. The applied resource management techniques are presented and discussed. The talk concludes with some visions on the Dark Silicon problem.

Assisting Run-time Optimization of Many-Core Systems by Design-time Characterization
Prof. Dr.-Ing. M. Glaß (FAU)

Recent research initiatives target future many-core systems where competing applications can adapt to dynamic usage scenarios and the type and number of available processing elements (PEs). Both the system and the application have functional and extra-functional objectives and constraints. However, the dynamics of the system prohibits static design-time optimization techniques. Instead, the run-time system needs to determine proper implementations of the applications while optimizing system-wide objectives and respecting constraints. We propose rigorous design-time characterization of applications to assist the run-time system by generating implementation variants for applications which are represented as Pareto curves with annotated objectives and architectural requirements and constraints. Based on this information, it is possible to systematically realize run-time systems which can foresee how the selection of implementation variants will influence system-wide objectives and constraints.

Resource Aware Programming with Invasive MPI
I. Compres Urena (TUM)

Because of the number of cores and hardware threads in modern CPUs, performance today is closely tied to the available parallelism in applications. This parallelism changes at different phases of a program and is typically input dependent. In spite of this, MPI applications today are launched with a fixed number of processes, and lose efficiency as a consequence. Ideally, a program would adjust its used of resources based on the available parallelism at runtime, achieving higher power efficiency and performance. The invasive programming model aims to allow for such resource aware applications. Invasive MPI (iMPI) is a message passing library that is optimized and extended to support the invasive programming model. In this presentation, existing functionality is described and future improvements proposed.

Workshop on Dynamic co-optimization of applications and resource management (HiPEAC Computer Systems Week 2014)

May 13, 2014, Barcelona, Spain: Prof. Dr. Michael Gerndt (TUM) and Dr. Josef Weidendorfer (TUM) organize the first Workshop on Dynamic co-optimization of applications and resource management at HiPEAC Computer Systems Week 2014. Optimal utilization of available resources is a major challenge in the scope of the raising complexity of todays' computer systems consisting of multicore and accelerator components. For best efficiency, both in terms of performance and power consumption, it may be useful to run multiple applications with different resource demands simultaneously, and take their scalability characteristics into account when they compete for available compute and communication capabilities. For best decisions, scheduling algorithms should know about dynamic applications demands and characteristics, and applications may be able to tune their execution if they get notified about scheduling decisions. Such strategies should improve system efficiency in general, but even more so for HPC systems, which currently do not run multiple user jobs simultaneously.
This thematic session wants to bring together research teams and users both from embedded and HPC fields, to discuss different solutions to more efficient resource utilization proposed in various currently running research activities, to trigger new ideas, and to build new connections for upcoming research activities in this context. more information

Inaugural lecture: "Maßschneiderbare Systemsoftware"

April 17, 2014, Erlangen (FAU): Dr.-Ing. Lohmann (FAU) gave his inaugural lecture on "Maßschneiderbare Systemsoftware" at "Tag der Informatik".

Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES)

March 28, 2014, Dresden, Germany: Prof. Dr.-Ing. Stechele from the Technical University of Munich (TUM) organizes a Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES) at the DATE14. The scope of the workshop is to address challenges of embedded portable software development on multi-core structures related to various performance aspects, power efficiency, correctness and reliability including aging. more information

Special Day on System Level Design at DATE 2014

March 26, 2014, Dresden, Germany: Prof. J. Teich, FAU and J. Stahl, Synopsys, Co-Chairs of the DATE 2014.
“The exploitation of recent technology achievements such as more and more processor cores and other IP modules available on a chip today is currently of big interest to many developers in application areas of embedded systems such as automotive, industrial automation and avionics. But there are also very challenging expectations on the achievable improvements and on the available support by tool vendors and system houses to aid handling this increasing system complexity”, says Jürgen Teich, co-chair of the DATE 2014 Special Day on System Level Design. This special day will therefore reflect current industrial practices as well as present recent advances in the System Level Design research area. A particular emphasis will be on ultra-low power design and modeling at multiple abstraction levels, virtual platforms for software development and architecture design of MPSoCs. A panel on “HW/SW Co-Development – The Industrial Workflow” will take place in the afternoon to discuss opportunities and challenges of joint hardware and software development. Moreover, two hot-topic sessions in the morning on “The fight against Dark Silicon” and “Predictable Multi-Core Computing”, and a special session on “System Simulation and Virtual Prototyping” in the afternoon will comprise this special day’s schedule. A particular highlight of the day is the special day´s keynote speech by Dr. Michael Bolle (Executive Vice President Engineering, Bosch), talking about the “Auto cockpit of the future”. more information

International Workshop on Multi-Objective Many-Core Design (MOMAC)

February 25-28, 2014, Luebeck, Germany: Stefan Wildermann and Michael Glass (FAU) are organizing the First International Workshop on Multi-Objective Many-Core Design (MOMAC) at the ARCS 2014.
more information

Session at Embedded World Conference, February 25, 2014, Nuremberg:
Multicore processors for embedded systems: Are we ready?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich participated in this years Embedded World Conference as a speaker on the panel "Multicore processors for embedded systems: Are we ready?" (Session 9). The main focus of the discussion with other multicore experts were the future plans of processor vendors, the challenges of multicore processors in the embedded systems area and important research results that help to face these challenges. » more information.

Events 2013

Keynote Talk, November 25, 2013, MCC13:
Invasive Computing - The Quest for Many-Core Efficiency and Predictability

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Halmstad, Sweden, November 25, 2013: Professor Teich has been invited as a keynote speaker at MCC 13, the 6th Swedish Workshop on Multicore Computing, see » http://www.hh.se/mcc13 in Halmstad, Sweden. He gave an overview of the accomplishments of the Transregional Research Centre Invasive Computing (SFB/TR89) during its first funding phase.

1st International Workshop on Multicore Application Debugging (MAD 2013)

Munich, Germany, November 14-15, 2013: Prof. Dr. Herkersdorf (TUM), Prof. Leupers (RWTH Aachen) and Prof. Chakraborty (TUM) are organizing the First International Workshop on Multicore Application Debugging (MAD 2013) at the TU in Munich . » more information.

Invited Talk, November 11, 2013, University of Exeter, UK:
Parallelisation of dynamically changing grids with a cluster-based approach and invasion

Dipl.-Inf. Martin Schreiber (Informatics V — Scientific Computing, TUM)

Dipl.-Inf. Martin Schreiber gave a talk at the College of Engineering, Mathematics and Physical Sciences (University of Exeter) during his research internship in the UK. » more information.

Invited Talk, November 6, 2013, Imperial College, UK:
Parallelisation of dynamically changing grids with a cluster-based approach and invasion

Dipl.-Inf. Martin Schreiber (Informatics V — Scientific Computing, TUM)

Dipl.-Inf. Martin Schreiber gave an invited talk at the Imperial College (London, UK).
The efficient execution of numerical simulations with dynamical adaptive mesh refinement (DAMR) belongs to one of the major challenges in HPC. With simulations demanding for a steadily changing grid structure, this imposes efficiency requirements on handling that structure as well as managing connectivity and simulation data stored on the grid. Large-scale HPC systems furthermore lead to additional requirements such as load-balancing and thus data migration on distributed-memory systems which are non-trivial for simulations running with DAMR.
The first part of the talk focuses on the optimization and parallelization of DAMR simulations and the second part of the talk is on the optimization of parallelization models currently assigning computational resources statically during program start.

Invited Talk, October 30, 2013, tubs.CITY :
Managing Change and Autonomy for Critical Applications

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at the occasion of the annual Symposium of tubs.CITY, the Center for Informations and Information Theory of the University of Braunschweig, Germany.

Dr.-Ing. Stefan Wildermann is honored with the doctoral award of the STAEDTLER Stiftung.

October 28, 2013: Seit 15 Jahren vergibt die STAEDTLER-Stiftung jährlich 10 Promotionspreise an Doktoranden der Friedrich-Alexander-Universität Erlangen-Nürnberg für außergewöhnliche Leistungen. In diesem Jahr erhält Dr. Stefan Wildermann einen der Promotionspreise der STAEDTLER-Stiftung für seine Doktorarbeit mit dem Titel "Systematic Design of Self-Adaptive Embedded Systems with Applications in Image Processing".

Invited Talk, September 30, 2013, ESWEEK, Canada:
The Invasive Computing Paradigm as a Solution for Highly Adaptive and Efficient Multi-core Systems

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Teich gave an invited talk at the Special session: "Run-Time Adaptation for Highly-Complex Multi-Core Systems" at ESWEEK in Toronto.
» more information.

Special Session at ESWEEK, September 30, 2013, Montreal, Canada:
Run-Time Adaptation for Highly-Complex Multi-Core Systems

organised by Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT)

A special session on the topic of "Run-Time Adaptation for Highly-Complex Multi-Core Systems" has been organised by Prof. Dr.-Ing. Jörg Henkel for presentation at ESWEEK in Toronto during the International Conference on Hardware/Software Codesign and System Synthesis (CODESISSS). see » http://esweek.acm.org/codesisss.

Lange Nacht der Wissenschaften 2013 (FAU)

At the Embedded Systems Initiative (ESI) booth at the Science Night 2013, Carolin Böhm-Reichert, Sascha Roloff and Dr. Torsten Klie gave an overview about the current research vision of Invasive Computing, which lets applications demand processors and the computer tries to fulfill them. Under the motto „Friendly Invasion of Processors”, we explained how the workload of several applications can be distributed to more than 100 processors in a fair way.
see »more information.

Jürgen Becker ist Ehrendoktor der TWU Budapest

June 2013, TWU Budapest, Hungary: Professor Jürgen Becker, der am Karlsruher Institut für Technologie (KIT) das Institut für Technik der Informationsverarbeitung leitet, hat die Ehrendoktorwürde der Technischen und Wirtschaftswissenschaftlichen Universität (TWU) Budapest erhalten. Die Hochschule zeichnet ihn damit für seine Forschung zu Eingebetteten Systemen aus.

Best Paper Award for InvasIC Team at ASAP13

June 6, 2013, Washington, DC, USA: Prof. Teich (2nd to the right) is honored by receiving the best paper award for the contribution Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays at the 24th IEEE Int. Conference on Application-specific Systems, Architectures and Processors (ASAP13), Washington DC, USA.

Presentation at DAC 2013, June 2-6, 2013, Texas, USA:
Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs

Vahid Lari and Dr. Frank Hannig (Hardware/Software Co-Design, FAU)

Vahid Lari and Frank Hannig presented in the Designer Track at the 50th Design Automation Conference (DAC) their research on "Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs", a joint work of TCRC 89's projects "B2: Invasive Tightly-Coupled Processor Arrays", "Z2: Validation and Demonstrator", and Synopsys, Inc.
see » http://esweek.acm.org/codesisss.

Tag der Informatik 2013 at the University Erlangen-Nuremberg

April 26, 2013, Erlangen: The focus of this year's "Tag der Informatik" at the FAU is on "Cyber-Physical Systems".
» Program

Invited Talk, April 25, 2013, The 20th annual ASCI Computing Workshop - GNARP 2013 (Leiden, the Netherlands)
Keynote Talk: Invasive Computing - The Quest for Many-Core Efficiency and Predictability

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main goal of "Invasive Computing" is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects. Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources. The result of an invasion phase is a so-called claim of resources. After termination of computational demanding phase, the application may then release the resources again back to the pool in a phase called retreat. Now, through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties becomes possible as well. In the talk, we provide a first language definition and for invasive computing based on X10 as developed by IBM. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization. Finally, a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of the video processing algorithm to be executed as a QoS tradeoff with image quality.

Invited Talk, April 24, 2013, The University of Amsterdam, the Netherlands
More Cores = Less Predictability?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Multi-core technology has become affordable and is offering enourmous opportunities not only with respect to high speed processing data processing, but also for power savings and other objectives.
However, in emerging application domains such as embedded data and reactive processing, maximizing average performance for which these systems have been typically designed for, is not at all the goal. For hard deadline or guaranteed throughput processing, it turns out that available architectures and tools for their programming may introduce a worse predictability than single core systems due to the interference of multiple applications or threads on the same and neighbor cores sharing common resources such as memory, cache, and due to affects resulting from OS service levels such as thread schedulers.
We propose a new paradigm called "invasive computing" and show how to achieve the required predictability for multi-core processing im embedded systems by providing resource isolation on demand. Fundamental changes involve language, compiler, and architecture design.

Invited Talk, April 18, 2013, Innovation Forum Smart Systems, BICCNet:
More Cores = Less Predictability?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

The innovation Forum Smart is organised by the Bavarian Information and Communication Technology Cluster (BICCNet). » more information

Presentation at DATE 2013, March 18-22, 2013, Grenoble, France:
Resource-aware Video Processing on Tightly-Coupled Processor Arrays

Vahid Lari and Dr. Frank Hannig

Invasive Computing was represented with multiple contributions at DATE 2013. Amongst technical presentations, Vahid Lari (FAU) had a demonstration at DATE'13 University Booth on "Resource-aware Video Processing on Tightly-Coupled Processor Arrays". Here, a prototype of a 5x5 tightly-coupled processor array (TCPA) was demonstrated using a Synopsys CHIPit prototyping platform. The demonstration shows how an invasive image processing application can adapt its quality of image filtering while keeping a fixed level of output throughput (as an application requirement). More specific, an input video stream is fed to the CHIPit system, through a DVI extension board, and processed by the TCPA and then, the output is shown on a display. The targeted applications on the invasive TCPA prototype are several real-time 1-D and 2-D image filters on a streaming input video. Here, based on the number of available PEs in the TCPA, a suitable 2-D edge detection or Gaussian filtering kernel is loaded.
» more information

10th anniversary of Department of Computer Science 12 (Hardware-Software-Co-Design) at FAU

March 8, 2013, FAU: The 10th anniversary of the Department of Computer Science 12 (headed by Prof. Dr.-Ing. Jürgen Teich) will be celebrated on 8th of March 2013. Prof. Franz-Josef Rammig (Heinz Nixdorf Institut, Universität Paderborn) will give the plenary lecture on "Autonomie, Adaptivität, Selbstorganisation: Auf dem Weg zu Cyber Physical Systems".
» Program

Invited Talk, February 24, 2013, "10th Workshop on Optimizations for DSP and Embedded Systems" (Shenzhen, China)
Keynote Talk: Resource-Aware Computing on Domain-Specific Accelerators

Dr.-Ing. Frank Hannig (Hardware/Software Co-Design, FAU)

The continuous progress in semiconductor technology allows for more and more complex processors architectures. The downside of these technological advances is that computing has hit already a power and complexity wall. These days, energy efficiency has become more important than pure computing power. That means, in order to scale computing performance in the future, systems' energy efficiency has to be significantly improved. The design of heterogeneous hardware with different specialized resources, such as accelerators dedicated for one application domain is a promising solution to address this challenge. In this talk, I introduce a class of domain-specific programmable accelerators. In addition, techniques for increasing their energy efficiency as well as resource-aware programming approaches and symbolic mapping techniques for such massively parallel systems are presented.

Invasive Computing News in HPC Wire: "The Week in HPC Research"

February 21, 2013: Invasive Computing has received considerable attention in the HPC community. A contribution by Michael Bader, Hans-Joachim Bungartz, and Martin Schreiber has found mentioning in a news article of HPC Wire under » www.hpcwire.com

Keynote Talk, February 20, 2013, ARCS 2013 (Prague, Czech Republic)
Invasive Computing - The Quest for Many-Core Efficiency and Predictability

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main goal of "Invasive Computing" is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects. Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources. The result of an invasion phase is a so-called claim of resources. After termination of computational demanding phase, the application may then release the resources again back to the pool in a phase called retreat. Now, through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties becomes possible as well. In the talk, we provide a first language definition and for invasive computing based on X10 as developed by IBM. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization. Finally, a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of the video processing algorithm to be executed as a QoS tradeoff with image quality.

Dagstuhl-Seminar 13052: Multicore Enablement for Embedded and Cyber Physical Systems, Jan. 27th - Feb. 1st 2013, Schloss Dagstuhl

Prof. Herkersdorf, Prof. Hinchey (University of Limerick) and Prof. Paulitsch (EADS Deutschland)

Professors Herkersdorf (TUM), Hinchey (University of Limerick) and Paulitsch (EADS Deutschland) are organising the Seminar "Multicore Enablement for Embedded and Cyber Physical Systems" in Schloss Dagstuhl. An Abstract of the Seminar is availabel » here.

Events 2012

Presentation at ReConFig 2012,December 5-7, 2012, Cancun, Mexico:
Adaptive Application-Specific Invasive Microarchitecture demonstrator

Carsten Tradowsky (KIT)

Carsten Tradowsky presents an Adaptive Application-Specific Invasive Microarchitecture demonstrator at the 2012 International Conference on ReConFigurable Computing and FPGAs demo night. Additionally, a presentation on the invasive hardware architecture was given.

Workshop at ICCAD, November 8, 2012, San Jose, California:
1st International Workshop on Domain-Specific Multicore Computing

organised by Prof. Teich (FAU) and Prof. Vijay Narayanan (Penn State University)

Prof. Teich (FAU) and Prof. Vijay Narayanan (Penn State University) are organising the 1st International Workshop on Domain-Specific Multicore Computing at ICCAD 2012. The progam is available as » pdf.

Invited Talk, Friday, October 26, 2012, IBM Böblingen:
Invasive Computing - or - How to Tame 1000+ Cores on a Chip?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main idea of "Invasive Computing" relies on the vision to make application-developers conscious of the temporal computational demands of their programs and that these should be able to spread their load at run-time on processors, communication and memory resources themselves in phases called invasion. First, a language definition and implementation for invasive computing based on X10 as developed by IBM is given. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization.

Invited Talk, Monday, October 15, 2012, HiPEAC Computing Systems Week (Ghent, Belgium):
Models and Assistive Tools for Programming Emerging Architectures

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

At the HiPEAC Computing Systems Week 2012 InvasIC discusses common ties and interdisciplinary cooperation with several EU-funded research projects on models and tools for programming emerging multicore architectures (HiPEAC CSW).

• » Program.

Invited Talk, Friday, September 28, 2012, Paris (UPMC, LIP6):
Invasive Computing: A Systems-Programming Perspective

Prof. Dr.-Ing. Wolfgang Schröder-Preikschat (Distributed Systems and Operating Systems, FAU)

Invasive Computing is a research program that aims at developing a new paradigm to address the hardware- and software challenges of managing and using massively-parallel MPSoCs of the years 2020 and beyond. The program encompasses twelve projects from the areas of computer architecture, system software, programming systems, algorithm engineering and applications. The core idea is to let applications manage the available computing resources on a local scope and to provide means for a dynamic and fine-grained expansion and contraction of parallelism. This talk provides a brief overview of the program and presents initial thoughts on system software support for it.

• Handout

Invited Talk, Thursday, September 20, 2012, Intel Braunschweig:
Prof. Dr.-Ing. Jürgen Teich and Richard Membarth (Hardware/Software Co-Design, FAU)

Prof. Dr.-Ing. Jürgen Teich:
Invasive Computing - or - How to Tame 1000+ Cores on a Chip?

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main idea of "Invasive Computing" relies on the vision to make application-developers conscious of the temporal computational demands of their programs and that these should be able to spread their load at run-time on processors, communication and memory resources themselves in phases called invasion. First, a language definition and implementation for invasive computing based on X10 as developed by IBM is given. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization.

Richard Membarth:
Automatic Code Generation for Image Processing Algorithms on Accelerators in Heterogeneous Architectures

This talk presents the Heterogeneous Image Processing Acceleration (HIPAcc) Framework that allows automatic code generation for algorithms from the domain of medical imaging. By decoupling the algorithm from its schedule in a domain-specific language, efficient code can be generated that leverages the computational power of accelerators such as GPUs. The decoupling allows to map the algorithm to the deep memory hierarchy found in today's GPUs based on domain knowledge and an architecture model of the target machine. Based on the same algorithm description, tailored code variants can be generated for different target architectures, improving programmer productivity significantly.

Special Session at FDL 2012, September 18, 2012, Wien, Austria:
Invasive Programming of Heterogeneous Multi-Core Systems

organised by Christian Haubelt (University of Rostock)

Prof. Jürgen Teich (FAU), Marcel Meyer (TUM) and Prof. Michael Gerndt (TUM) present the Transregio in a Special Session on "Invasive Programming of Heterogeneous Multi-Core Systems" at FDL 2012.

» Program

Invited Talk, Thursday, August 9, 2012, Department of Electrical and Computer Engineering, University of Auckland:
Invasive Computing - or - How to Tame 1000+ Cores on a Chip?

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of many concurrent applications can obviously not be organized in a fully centralized way any more as it is done in today’s multi-core processor systems. Also, feature variations are expected to become a severe problem threatening not only performance but also correctness of computations. One way shown how be able to cope with an expected increase of run-time uncertainties is to exploit flexibility of as well the code to be executed as the reconfigurability of the underlying hardware resources. The only major question is at what price this can and should be done, to what degree, and in the control of whom such adaptations shall take place. In this introductory talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main idea of "Invasive Computing" relies on the vision that application-developers are typically conscious of the temporal computational demands of their programs and that these should be able to spread their load at run-time on processors, communication and memory resources themsolves in phases called invasion. Resource-awareness, on the other hand, means that such decisions whether to invade or retreat from resources should be done in reflection with the state of the underlying resources such as temperature-, reliability-, aging-, or fault-monitor information. As an example, spawning more and more threads to an already overloaded MPSoC CPU architecture might lead to less performance than choosing an alternative sequential or approximate computation. In July 2011, the German Research Foundation (DFG) has estalished its transregional collaborative research center TR89 on "Invasive Computing" with Erlangen (FAU), Karlsruhe (KIT) und Munich (TUM) as the three participating research universities with the goal to investigate the paradigm of "Invasive Computing" intensively with respect to the development of new programming and language concepts, architectures of invasible resources, simulation and compiler support as well as application and demonstrator development. Here, we give an overview of the basic principles of "Invasive Computing". In particular, we present a first language definition and implementation for a set of new and not yet existing parallel programming constructs on top of the language X10 as developed by IBM. Also, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, memory organization, etc. It will be finally outlined how and to what degree we may expect invasive computing to improve fault-resilience, scalability, efficiency and resource utilization by the analysis of invasive speedup and efficiency numbers.

Carsten Tradowsky, Florian Thoma, Michael Hübner and Jürgen Becker receive the Best Work-in-Progress Paper Award on the SIES 2012

June 22, 2012: Carsten Tradowsky, Florian Thoma, Michael Hübner and Jürgen Becker receive the Best Work-in-Progress Paper Award for their paper "SPARC: Using an Architrecture Description Language Approach for Modelling an Adaptive Processor Microarchitecture" on the 7th IEE International Symposium on Idustrial Embedded Systems (SIES) 2012.

40th anniversary of Department of Computer Science 4 (Distributed Systems and Operating Systems) at FAU

The 40th anniversary of the Department of Computer Science 4 (headed by Prof. Dr.-Ing. Schröder-Preikschat) will be celebrated on June 29, 2012.
» Program

Prof. Teich visits Dr. Matthias Sauer, Director at Apple, Cupertino, CA.

June 01, 2012: Prof. Teich visits Dr. Matthias Sauer, Director at Apple, Cupertino, CA.­­­

Invited Talk, Fri, May 18, 2012, Hong Kong:
i-Core: Adaptive Computing for Multi-core Architectures

Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT)

Tag der Informatik 2012 at the University Erlangen-Nuremberg

April 20, 2012: The focus of this year's "Tag der Informatik" at the FAU is on "Going Parallel – Informatik im Multi-/Many-Core Zeitalter".
» Program

Michael Hübner is apppointed as professor at the Ruhr-Universität Bochum

Since April 2012 Prof. Dr.-Ing. habil. Micha­el Hüb­ner is the Chair for Em­bed­ded Sys­tems for In­for­ma­ti­on Tech­no­lo­gy (ESIT) at the Ruhr-Uni­ver­si­ty of Bo­chum (RUB).

Invited Talk, March 16, 2012, Date 2012 (WS QVVP12), Dresden:
Actor-Based Virtual Prototype Generation

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Abstract—In this talk, we present a solution to generate virtual prototypes from actor-based application models. Generating virtual prototypes from formal application models allows for a two-part design flow: (1) model-specific optimization and automatic design space exploration techniques may be applied to the formal application model; (2) tools and processes established for implementation-oriented virtual prototypes then may be used to achieve to the final implementation. Here, we concentrate on automatic generating a virtual prototype from a formal actor-based application model. Additionally, we highlight an opportunity of such an automatic generation: By sustaining the link between the formal application model and the generated prototype, the formal model may be further exploited in virtual prototype simulation. As a demonstration, we show how this link may be used to accelerate the simulation of an automatically generated SystemC/TLM prototype of a network packet filter by up to 30%.

Invited Talk, Febuary 29, 2012, ARCS 2012 (WS PARMA), Munich:
Introduction to invasive computing and overhead analysis for a shared-memory MPSoC

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

This talk introduces a novel paradigm for the organization of concurrent applications for future many-core systems with thousands or more processing elements called "Invasive Computing". The main idea of this approach is that the application developer is aware of the underlaying resources and reserves these resources explicit with the command invade, distributes the workload with the command infect and frees the resources with the command retreat. The talk also presents an analysis of the performance overheads of invasive computing applications on shared-memory MPSoC architectures. The nature of these is to claim and free resources dynamically at run-time to increase resource efficiency of future MPSoC architectures while not sacrificing speedup in comparison to traditional, statically mapped applications. This holds true especially for programs with highly dynamic parallelism profiles. Based on a formal notation of speedup and resource efficiency for invasive parallel programs, we present a real SPARC LEON-based MPSoC system implementation to evaluate achievable resource efficiencies for realistic workload scenarios showing that the real-measured overhead of invasion can be kept very low and resource efficiencies of up to 100% will become possible without a considerable drop in speedup compared to non-invasive programs using statically allocated resources.

Tamim Asfour is apppointed as professor at the KIT

Since Febuary 2012 Prof. Dr.-Ing. Tamim Asfour­­ is the Chair for Humanoide Robotik Systems at the Karlsruhe Institut ­of Tech­no­lo­gy ­­­­(KIT).

Events 2011

Leibniz-Preis für Peter Sanders

December 08, 2011: Professor Peter Sanders vom Karlsruher Institut für Technologie (KIT) erhält den renommierten Gottfried Wilhelm Leibniz-Preis der Deutschen Forschungsgemeinschaft (DFG) für das Jahr 2012. Der Leibniz-Preis ist mit 2,5 Millionen Euro der international höchstdotierte Wissenschaftspreis. Seit 2004 forscht und lehrt Sanders am KIT. Der Wissenschaftler ist auf internationaler wie auf nationaler Ebene eine der Schlüsselfiguren des Algorithm Engineering.

Mitglieder des SFB/Transregio 89 in DFG-Fachkollegien gewählt

December 08, 2011: Prof. Andreas Herkersdorf (TUM) und Prof. Dr.-Ing. Jörg Henkel (Chair for Embedded Systems, KIT) wurden in das Fachkollegium "Informatik – Rechnerarchitekturen und eingebettete Systeme" sowie Professor Wolfgang Schröder-Preikschat (FAU) in das Fachkollegium "Informatik – Betriebs-, Kommunikations- und Informationssysteme" der DFG für die Amtsperiode 2012 bis 2015 gewählt.

Invited Talk, November 15, 2011 at TUM:
Frameworks for Multi-core Architectures and GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration

Richard Membarth (FAU) and Wieland Eckert (Siemens Healthcare Sector, Forchheim)

Developing software for multi-core systems and in particular for GPU accelerators imposes major challenges to programmers in medical imaging: in what way should we manage the available resources, divide and distribute the workload, and how can we handle problems arising in parallel processing like race conditions? As a possible remedy, parallelization frameworks have been proposed that relieve the programmer from such low-level tasks. In this talk, we present the evaluation of frameworks for programming multi-core processors and GPU accelerators. Using the 2D/3D image registration as case study, we analyze different aspects of each framework like usability, performance, and parallelization overhead.

Neues Graduiertenkolleg "Heterogene Bildsysteme"

November 14, 2011: Die DFG richtet das neue GRK 1773 an der der Universität Erlangen-Nürnberg ein, in dem heterogene Bildsysteme geplant, entwickelt und realisiert werden sollen. Systeme zur Verarbeitung, Erzeugung und Übertragung digitaler Bilder unterliegen sehr oft hohen Anforderungen mit Blick auf Rechenleistung, Datendurchsatz oder Kosten. Das zeigen etwa Beispiele aus der medizinischen Bildverarbeitung oder Computerspielanwendungen. Die Bildsysteme sind in zweierlei Hinsicht heterogen: Zum einen ist innerhalb eines Systems die Berechnung auf mehrere verschiedenartige Komponenten verteilt, zum anderen gibt es eine große, heterogene Menge an Architekturen, auf denen unterschiedliche Bildanwendungen laufen sollen. Beide Arten von Heterogenität sollen im Graduiertenkolleg erforscht werden. Sprecher des Graduiertenkollegs ist Professor Marc Stamminger. Des Weiteren sind u. a. noch folgende Wissenschaftler, die auch im SFB/Transregio 89 involviert sind, an dem neuen GRK beteiligt: Dr. Frank Hannig, Dr. Daniel Lohmann, Professor Wolfgang Schröder-Preikschat und Professor Jürgen Teich.

Treffen auf der Embedded Systems Week

October 10, 2011: Ehemalige (Studenten, Postdocs und Visiting Scholars) von Prof. Edward A. Lee, UC Berkeley, treffen sich auf der Embedded Systems Week (ESWEEK) 2011 in Taipeh, Taiwan.
Prof. Teich verbrachte das Jahr 1994 als Postdoktorand der Deutschen Forschungsgemeinschaft (Visiting Scholar) in der Ptolemy-Forschergruppe von Prof. Lee.

Prof. Teich elected Member of Academia Europaea, the Academy of Europe"

September 24, 2011: Herr Professor Dr.-Ing. Jürgen Teich, Inhaber des Lehrstuhls für Hardware-Software-Co-Design an der Friedrich-Alexander-Universität Erlangen-Nürnberg, wurde zum Mitglied der Academia Europaea (AE), the Academy of Europe, gewählt.
Mitglieder der Academia Europaea sind u. a. führende Wissenschaftler aus den Gebieten Physik, Biologie, Medizin, Mathematik, Literaturwissenschaften, Geisteswissenschaften, Sozialwissenschaften, Kognitionswissenschaften, Wirtschaftswissenschaften und Rechtswissenschaften.
Die Berufung zum Mitglied ist eine große Ehre und Anerkennung für die herausragenden Leistungen von Herrn Professor Teich auf dem Gebiet der Informatik.

Keynote Talk, September 15, 2011 at FAU:
Invasive Parallel Computing - An Introduction

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Prof. Jürgen Teich gave a Keynote Talk at the 12th Colloquium of the DFG Priority Programme 1183 "Organic Computing" at FAU.

Invited Talk, September 9, 2011 at Universität zu Lübeck:
Invasive Parallel Computing - An Introduction

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Technology roadmaps foresee already today 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of many concurrent applications can obviously not be organized in a fully centralized way any more as it is done in today's multi-core processor systems. Also, feature variations are expected to become a severe problem threatening not only performance but also correctness of computations. One way shown how be able to cope with an expected increase of run-time uncertainties is to exploit flexibility of as well the code to be executed as the reconfigurability of the underlying hardware resources. The only major question is at what price this can and should be done, to what degree, and in the control of whom such adaptations shall take place. In this introductory talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing". The main idea of "Invasive Computing" relies on the vision that application-developers are typically conscious of the temporal computational demands of their programs and that these should be able to spread their load at run-time on processors, communication and memory resources themsolves in phases called invasion. Resource-awareness, on the other hand, means that such decisions whether to invade or retreat from resources should be done in reflection with the state of the underlying resources such as temperature-, reliability-, aging-, or fault-monitor information. As an example, spawning more and more threads to an already overloaded MPSoC CPU architecture might lead to less performance than choosing an alternative sequential or approximate computation. In July 2011, the German Research Foundation (DFG) has estalished its transregional collaborative research center TR89 on "Invasive Computing" with Erlangen (FAU), Karlsruhe (KIT) und Munich (TUM) as the three participating research universities with the goal to investigate the paradigm of "Invasive Computing" intensively with respect to the development of new programming and language concepts, architectures of invasible resources, simulation and compiler support as well as application and demonstrator development. Here, we give an overview of the basic principles of "Invasive Computing". In particular, we present a first language definition and implementation for a set of new and not yet existing parallel programming constructs on top of the language X10 as developed by IBM. Also, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, memory organization, etc. It will be finally outlined how and to what degree we may expect invasive computing to improve fault-resilience, scalability, efficiency and resource utilization by the analysis of invasive speedup and efficiency numbers.

Prof. Teich wird zum Associate Editor (AE) bestellt"

Prof. Dr.-Ing. Jürgen Teich (Lehrstuhl für Hardware-Software-Co-Design) wird bestellt zum Associate Editor (AE) der Zeitschrift ACM Transactions on Design Automation of Electronic Systems (TODAES), siehe http://todaes.acm.org

Invited Talk, July 25, 2011 at Stanford University (USA):
Invasive Parallel Computing - An Introduction

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Invited Talk, July 22, 2011 at Par Lab, UC Berkeley, USA
Invasive Parallel Computing - An Introduction

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Abstract here
 
 

Events 2010

Invited Talk, October 28, 2010, CASA 2010 at Scottsdale, USA:
Invasive Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Invited Talk, August 9, 2010 at The University of Sydney, Australia:
Invasive Computing — An Overview

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Invited Talk, August 6, 2010, National University of Singapore (NUS):
Invasive Computing - A Novel Paradigm for Parallel Computing

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

ASAP 2010 in Rennes (Frankreich)

July 07-09, 2010: Die 21. IEEE International Conference on Application-specific Systems, Architectures and Processors, kurz "ASAP 2010", wurde in diesem Jahr von Prof. Teich mit organisiert.
Ausführliche Informationen zur Konferenz finden Sie auf den Webseiten der ASAP 2010.

Start des DFG Sonderforschungsbereich/Transregio 89

July 01, 2010: Sprecherhochschule ist die Friedrich-Alexander-Universität Erlangen-Nürnberg, Sprecher ist Herr Professor Dr.-Ing. Jürgen Teich. Weitere antragstellende Hochschulen sind das Karlsruher Institut für Technologie und die Technische Universität München.

Invited Talk June 13, 2010 at Design Automation Conference (DAC), USA:
Invasive Computing — A Novel Parallel Computing Paradigm

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Invited Talk, April 9, 2010 Frankfurt am Main (30. Sitzung Leitungskreis der Fachgruppe RSS (Rechnergestützter Schaltungs- und Systementwurf), VDE):
Invasives Rechnen

Prof. Dr.-Ing. Jürgen Teich (Hardware/Software Co-Design, FAU)

Verleihung des Humboldt-Forschungspreises an Prof. Dr. Zoran Salcic

March 19, 2010: Im Rahmen der Verleihung des Humboldt-Forschungspreises in Bamberg überreichte Prof. Dr. Helmut Schwarz, Präsident der Alexander-von-Humboldt-Stiftung, heute die Urkunde an Prof. Dr. Zoran Salcic von der University of Auckland, Neu-Seeland. Prof. Salcic ist derzeit Gastprofessor am Lehrstuhl von Prof. Dr.-Ing. Jürgen Teich.

Press

• April 23, 2020: Festgestellt: Gender Gap in der Informatikforschung (Meldung der FAU)
• July 24, 2019: Run for Fun - InvasIC at the B2 Run 2019 (Meldung der FAU auf Facebook)
• July 24, 2019: Run for Fun - InvasIC at the B2 Run 2019 (Meldung der FAU)
• May 22, 2018: 10 Millionen Euro für Invasive Prozessorsysteme (Pressemitteilung der FAU)
• May 18, 2018: DFG fördert 14 neue Sonderforschungsbereiche (Pressemitteilung der DFG)
• December 2014: Effizientes Rechnen mit heterogenen Multi-Cores (LookKIT 04/2014, page 19)
• January 2014: Invasives Rechnen macht Computer effizienter (TUMcampus, page 19)
• December 2013: Invasion der Prozessoren (Offizieller Newsletter der Embedded Systems Initiative Erlangen-Nürnberg, page 4)
• November 2013: Invasion der Prozessoren (alexander 92, page 10)
• October 2010: Autonom und anpassungsfähig (FAU uni | kurier | aktuell, 5)
• June 30, 2010: DFG fördert Entwicklung effizienterer Multiprozessorensysteme (idw-online.de)
• June 30, 2010: DFG fördert Entwicklung effizienterer Multiprozessorensysteme (academics.de)
• June 30, 2010: DFG fördert Entwicklung effizienterer Multiprozessorensysteme (innovations-report.de)
• June 30, 2010: DFG fördert Entwicklung effizienterer Multiprozessorensysteme (uni-protokolle.de)
• May 28, 2010: DFG bewilligt Förderung des SFB-Transregio 89 »Invasive Computing« (informatik.kit.edu)
• May 19, 2010: DFG bewilligt Förderung des SFB-Transregio 89 »Invasive Computing« (Pressemitteilung der DFG)