Projects

B1: Adaptive Application-Specific Invasive Microarchitecture

Principal Investigators:

Prof. J. Henkel, Prof. J. Becker, Dr. L. Bauer

Scientific Researchers:

M. Damschen, T. Harbaum

Abstract

Project B1 investigates mechanisms that provide run-time adaptivity in the microarchitecture (μArch) and by using a run-time-reconfigurable fabric. The goals are to advance the concepts of state-of-the-art reconfigurable processors towards invasion and to exploit their benefits in the invasive computing project. We propose concepts and methods that allow invading the reconfigurable fabric and μArch within the invasive core (i-Core). The focus is to (i) investigate run-time adaptivity at the μArch level (e.g. dynamic L1 cache size or branch prediction) and (ii) provide so-called Special Instructions (SIs, implemented by i-let-specific accelerators) on demand.

The figure above provides an overview of the i-Core architecture as it was developed in the first funding phase. The instruction-set architecture is extended by additional instructions that allow the application developer to adapt the microarchitecture to be i-let specific. The adaptive μArch mechanisms include: adaptive branch prediction, adaptation of the pipeline length, and a dynamically parameterisable L1 cache. In addition to the SPARC V8 instruction set as implemented by the LEON3, the i-Core introduces SIs that are implemented by run-time-reconfigurable accelerators. The accelerators are loaded into reconfigurable containers, designated regions that support partial reconfiguration without disrupting the rest of the system. The reconfigurable containers are connected to an interconnect infrastructure that establishes communication between the accelerators and to the i-Core μArch, tile-local memory, and data cache. Building on top of the developed i-Core architecture, in Phase II we will contribute to the common goals of dark-silicon management (by improving the i-Core efficiency, which allows Project B3 spatial and temporal greying of cores without compromising performance) while at the same time offering predictability improvements (by constraining the i-Core adaptivity).

To improve the efficiency, we want to investigate an approach for automatic online SI generation that is transparent to the application developer. These so-called Auto-SIs may not reach the performance of offline-optimised SIs, but they are beneficial when an i-let that does not contain any regular SIs shall execute on an i-Core, e.g. when an i-let is migrated from a LEON3 to an i-Core. We also plan to move from a homogeneous to a heterogeneous reconfigurable fabric, with reconfigurable containers divided into different classes, offering a different amount and type of resources. To support it, we want to develop a heterogeneity-aware run-time system that exploits the efficiency of the reconfigurable fabric and allows optimised i-let invasions. In addition the contributions related to pure efficiency/dark silicon, we also offer trade-offs between efficiency and predictability as follows: We want to add a concept for intra-tile multicore invasion of the reconfigurable fabric, which allows LEON3 cores in an i-Core tile (i.e. a tile that contains an i-Core) to issue SIs to the i-Core. These so-called Remote-SIs execute on the reconfigurable fabric of the i-Core along with SIs executed by the i-Core itself. That increases the efficiency of the remote cores, but to sustain predictability of i-Core-SIs, the interference of Remote-SIs and i-Core-SIs can be limited at run time. Based on the findings of Phase I, we want to introduce Dynamic Intra-Tile Cache Reallocation, i.e. a flexible parameterisation and L1 cache allocation between the cores within a tile, to make more efficient use of the available on-chip memory resources. This allows improving the predictability, as each i-let can configure its desired cache configuration. In addition to the architectural/run-time contributions, we want to investigate compiler support for Offline SI Generation. To simplify SI creation, which was done manually in Phase I, we plan to provide compiler support (together with Project C3) to automatically identify suitable SI candidates for offline SI development.

Altogether, the above mentioned goals and novel contributions for Phase II improve the overall invasive computing system by increasing the efficiency and predictability of the i-Core and the i-Core tile. To enable application developers (Project D1 and Project D3), simulation (Project C2), characterisation, and pattern development (Project A4), agent system (Project C1), and dark-silicon management (Project B3) to simulate, estimate, and predict the performance of different i-Core features, we will develop and provide detailed i-Core performance models.

Synopsis

Building on top of the i-Core architecture developed in Phase I, the main focus of Project B1 in Phase~II is on efficient fabric invasion, intra-tile multicore support, and enhancing the usability. The main goal of the efficient fabric invasion and the intra-tile multicore support is to further increase the area efficiency of the i-Core, which directly contributes to the challenge of dark silicon, being a major topic in the second funding phase. Additionally, for all existing and new i-Core features that improve the efficiency by exploiting adaptivity, we will analyse and develop trade-offs between efficiency and predictability (at the cost of limited adaptivity). That means, if an i-let demands predictability, then not all i-Core features will be available for it and we will carefully analyse which features can still be used and provide models to improve the i-Core usability.

Approach

The i-Core can be invaded like regular LEON3 cores, but additionally the i-Core run-time system uses the invasive computing paradigm to manage its reconfigurable fabric. The following C code fragment shows how an H.264 Video Encoder i-let can be written to invade the reconfigurable fabric.
A comprehensive summary of the major achievements of the first funding phase can be found by accessing Project B1 first phase website.

H264_encoder() {
  // Set i-Core microarchitecture parameters
  set_i_Core_parameter(pipeline_length=7,
                       branch_prediction=2_2_correlation);
  // Invade a share of the reconfigurable fabric
  fabric_claim=invade(resource=reconf_fabric,
                      performance=trade_off_curve);
  while (frame=videoInput.getNextFrame()) {
    // Kernel: Motion Estimation
    // Special Instructions:
    //   Sum of Absolute Differences (SAD),
    //   Sum of Absolute Transformed Differences (SATD)
    SI_implementations=invade(resource=fabric_claim,
      SI={SAD, trade_off_curve[SAD], prediction[SAD]},
      SI={SATD, trade_off_curve[SATD], prediction[SATD]});
    infect(SI_implementations);
    execute_motion_estimation(frame, ...);
    ...
    // Kernel: Encoding Engine
    SI_implementations=invade(resource=fabric_claim, ...);
    infect(SI_implementations);
    execute_encoding_engine(frame, ...);
    ...
  }
}

In line 6, the i-let invades the reconfigurable fabric and receives a fabric claim, i.e. a subset of reconfigurable containers that can now be used by the i-let to reconfigure accelerators. The actual application consists of several kernels (Motion Estimation, etc.) that are executed sequentially for each frame. Before each kernel, the obtained fabric claim is further invaded by the SIs of the next kernel (lines 13 and 20). The SIs of a kernel compete for the reconfigurable fabric and this invade triggers the i-Core run-time system to choose the SI implementations, i.e. it decides which accelerators shall be reconfigured. The actual reconfiguration of accelerators is triggered by the infect call (lines 16 and 21). Infection is asynchronous, i.e. the actual kernel execute_motion_estimation() can start, while the accelerators are being loaded. SIs that do not yet have all accelerators loaded, are automatically emulated in software. Retreating from the fabric is implicit upon termination of the i-let.

A comprehensive summary of the major achievements of the first funding phase can be found by accessing Project B1 first phase website.

Publications