Projects

B1: Adaptive Application-Specific Invasive Micro-Architectures

Principal Investigators:

Prof. J. Henkel, Prof. J. Becker, Dr. L. Bauer

Scientific Researchers:

F. Lesniak, J. Höfer, H. Nassar

Abstract

Project B1 investigates mechanisms that provide run-time adaptivity in the micro-architecture (μArch) and by using a run-time reconfigurable fabric. In the first two funding phases, we advanced the concepts of state-of-the-art reconfigurable processors towards invasion, and we exploited their benefits in the invasive computing project. In particular, in Phase I, we proposed concepts and methods that allow invading the reconfigurable fabric and μArch within the invasive core (i-Core). We investigated run-time adaptivity at the μArch level (e.g. dynamic L1 cache configuration or branch prediction) and provided so-called Special Instructions (SIs; implemented by i-let-specific accelerators) on demand. In Phase II, we increased the performance of the i-Core even further (e.g. by generating SIs automatically on-the-fly), we investigated an intra-tile multicore support (the regular cores in the i-Core tile can now also use the reconfigurable fabric), we developed a dynamic intra-tile cache reallocation, and we also improved the usability of the i-Core (support for offline SI development and performance models for WCET analysis).

The figure above provides an overview of the i-Core architecture as it was developed in the first two funding phases. The μArch was provided with the new capability to allow the application developer to use i-let-specific adaptations. The adaptive μArch mechanisms include adaptive branch prediction, adaptation of the pipeline length, and a dynamically parameterisable L1 cache. In addition to the SPARC V8 instruction set, the i-Core introduces SIs that are implemented by run-time reconfigurable accelerators. The accelerators are loaded into reconfigurable containers, i.e. designated regions that support partial reconfiguration without disrupting the rest of the system. They are connected to an interconnect infrastructure that establishes communication between the accelerators and to the i-Core μArch, tile-local memory, and data cache.

Synopsis

Building on top of the developed i-Core architecture, the main focus in Phase III is in the realm of the common global and interdisciplinary research questions: Run-time requirement enforcement (e.g. analysing and enforcing WCETs and enforcing security requirements), and robust multi-objective optimisations (e.g. optimising for computational performance, memory performance, and configurable accuracy). For the first problem area, the interference of best-effort applications sharing an i-Core tile must be monitored and properly enforced such that static WCET analysis will always be valid for hard real-time applications. Building upon the results of Project C5, isolation concepts within the i-Core shall be leveraged to accomplish and enforce security requirements such as data integrity and bounded information leakage. For the second problem area, the concept of SIs shall be generalised to leverage approximate accelerators and to support complex control flow. A novel intra-tile memory reorganisation is envisioned in collaboration with Project B5 to provide dedicated access options between network adapter, tile-local memory (TLM), and cores. We will also continue our active collaboration with Project C3 about compiler-based SI generation.

Approach

In Phase III, Project B1 focuses on the common global and interdisciplinary research questions of run-time requirement enforcement (e.g. analysing and enforcing WCETs and enforcing security requirements), and robust multi-objective optimisations (e.g. optimising for computational performance, memory performance, and configurable accuracy). In the following, we explain the particular goals of the particular Working plan.

Timing analysis and enforcement

We plan to start by implementing the concepts of restartable and resumable SIs in our in-house i-Core simulator to learn more about their different performance/area trade-offs. Depending on the outcome, we will decide which alternative (might also be a combination of both) to focus on, and then we will implement it in hardware and integrate it in our stand-alone prototype. The cache analysis for reconfigurable caches and SIs that access the L1 cache shall be developed and integrated into OTAWA first. In a parallel effort, we will investigate how to modify/constrain aiT accordingly.

Intra-tile memory hierarchy reorganisation

In this WP, the current memory architecture will be reorganised. To find the best solution, several approaches must be thoroughly weighed up against each other. The current traffic on the bus has to be tracked and analysed, as well as the access of the i-Core to the TLM. Additionally, the architecture of the i-Core tile will be extended by the capability of near-data processing.

Control flow within special instructions

As the challenging parts will be on the tool side, we plan to start by carefully extending the data structures and interfaces of our tools for designing SIs and for analysing the worst-case execution time. After we are certain which is the best representation for the tools, we will start the actual tool development together with the required hardware modifications of the SI Execution Controller, predicate buses, and integration with COREFAB. In parallel, we will modify some prominent existing SIs (that were designed by manually unrolling loops) to use the new features for evaluation.

Approximated accelerators

In a first step, we will choose different applications according to their error-resilience and design an approximate accelerator for the GPP and an SI for the i-Core. Based on the first results, a higher-level-instance will be designed to initiate and track the usage of the approximate accelerator and the i-Core resources. Afterwards, the main task is to design an adaptive instance which can control the usage of the different hardware components at run time.

Information leakage protection

At first, we will introduce a statistical model based on the information flow of all channels of the cache subsystem. Afterwards, we will investigate our dynamic intra-tile cache reallocation with regard to security abilities. In parallel, we will work on implementing the different isolation mechanisms and their enforcers for the reconfigurable fabric. Afterwards, the TLM-MMU will be extended to provide access protection mechanisms.

Hardware support for compiler-based SI generation

We plan to start by investigating the area overhead for different numbers of Repack operations, to understand how many different modes we can afford. Then, we will extract the currently used modes and generalise them. The goal is that the used modes should be directly supported by Repack, whereas other modes may only be executable indirectly. For the generic accelerators, we will start by collecting suitable patterns from standard benchmarks to identify similarities and combine them to generic data paths.

Joint emulation, prototype, and demonstrator integration

All i-Core architecture innovations of Phase III will be developed and implemented in the WPs mentioned above. In this WP, we will at first integrate these features into our stand-alone FPGA prototype for development and testing purposes, and subsequently, we will integrate them into the ProDesign proFPGA demonstrator platform of Project Z2. We will use these prototypes for measurements and detailed evaluations. Together with all other projects, we will work on common demonstration scenarios and provide dedicated hardware acceleration for Project A4, Project D1, and Project D3.

A comprehensive summary of the major achievements of the first and second funding phase can be found by accessing Project B1 first phase and Project B1 second phase websites.

Publications